Physical Design Engineer (Backend Signoff and Reliability)

Texas Instruments; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Texas Instruments is seeking a Physical Design Engineer to work in Bengaluru, focusing on backend signoff and reliability. Candidates should have 2-5 years of experience with power grid planning, numerous Cadence tools, and backend signoff procedures to help shape the future of technology in the semiconductor industry.

Qualifications

• 2-5 years of experience in backend signoff and reliability.
• Hands-on experience in Innovus tool, Voltus, Tempus, and Pegasus/PVS.
• Experienced in full chip EMIR, SigEM, and Cell EM.

Responsibilities

• Conduct power grid planning and design at chip level.
• Manage signal and power bump planning and routing.
• Handle backend signoff flows including DRC, PERC, LVS, and ESD.

Skills

Power Grid planning

Custom routing

EMIR

Backend Signoff flows

Cadence tools

Job description

Physical Design Engineer (Backend Signoff and Reliability)

Physical Design Engineer (Backend Signoff and Reliability)

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Direct message the job poster from Texas Instruments

Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the world’s brightest minds, TI creates innovations that shape the future of technology. TI is helping about 100,000 customers transform the future, today. We’re committed to building a better future – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities and developing great minds. In TI’s Power Products, we’re developing breakthrough technology to power the world’s future innovations as well. Put your talent to work with us – change the world, love your job!

Embedded Processor Group is looking forward to hire Physical Design Engineer with experience in (Backend Signoff and Reliability)

Experience Level : 2-5 Years

• Power Grid planning and design at Chip level. Hands-on experience in Innovus tool to do custom routing for extremely stringent integration requirements.
• Signal and Power bump planning and routing
• Experience in full chip EMIR , SigEM and Cell EM
• Experience in Backend Signoff flows such as DRC , PERC ,LVS , Latup-Up , ESD etc
• Hands-on experience in Cadence tools like Innouvs, Voltus , Tempus and Pegasus/PVS

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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