Senior Synthesis and STA Engineer / Lead

Texas Instruments; India; On-site; INR 2,800,000 - 4,500,000; Full time

Job summary

A leading semiconductor company located in India is seeking a Senior STA and Synthesis Engineer / STA Lead to join their Connectivity engineering team. In this role, you will drive timing closure and synthesis optimization for advanced wireless connectivity SoCs, ensuring they meet performance, power, and area requirements. You will collaborate with design teams to enhance RTL and participate in groundbreaking connectivity innovations. The position offers opportunities for mentorship and exposure to diverse wireless standards and emerging technologies.

Qualifications

• Experience with static timing analysis and synthesis for connectivity SoCs.
• Ability to optimize RTL for timing, power, and area.
• Knowledge in developing synthesis methodologies and scripts.
• Hands-on with synthesis and STA methodologies.

Responsibilities

• Perform static timing analysis for connectivity SoCs.
• Collaborate with design teams for RTL optimization.
• Drive timing closure through coordination with physical design.
• Validate constraints with standard constraint checker tools.
• Coordinate timing closure through the physical design flow.
• Develop synthesis and STA methodologies and scripts.

Skills

Static timing analysis

Synthesis optimization

RTL optimization

Multi-technology expertise

DFT knowledge

Tools

Industry standard constraints checker tools

State-of-the-art EDA tools

Job description

Senior STA and Synthesis Engineer / STA Lead - Texas Instruments

About the Role

Join Texas Instruments' Connectivity engineering team as a Senior STA and Synthesis Engineer / STA Lead, where you'll play a critical role in delivering high-performance wireless connectivity solutions that power next-generation IoT, automotive, and industrial applications.

What You'll Do

Drive timing closure and synthesis optimization for advanced connectivity SoCs, ensuring our wireless solutions meet stringent performance, power, and area requirements across diverse market applications.

Technical Focus

• Multi-Technology Expertise: Work on synthesis and timing analysis across various wireless connectivity standards and protocols
• Full Flow Ownership: Drive synthesis, timing analysis, and optimization from RTL to layout handoff
• Performance Leadership: Ensure timing closure for complex mixed-signal connectivity designs

Key Responsibilities

• Perform static timing analysis and synthesis for connectivity SoCs
• Collaborate with design teams to optimize RTL for timing, power, and area
• Write SDC constraints across functional and DFT modes and validate the constraints through industry standard constraints checker tools
• Drive timing closure through physical design flow coordination
• Develop and maintain synthesis and STA methodologies and scripts

Growth Opportunities

• Work on both established connectivity platforms and breakthrough wireless technologies
• Contribute to multiple tape‑outs annually across different process nodes
• Influence next‑generation connectivity architecture decisions
• Mentorship opportunities with junior engineers and cross‑functional collaboration

Why This Role

• Direct impact on TI's wireless connectivity portfolio performance
• Exposure to diverse wireless standards and emerging technologies
• Opportunity to work with state‑of‑the‑art EDA tools and methodologies
• Be part of innovation initiatives including new wireless technologies for TI

Technical Environment

• Multiple process technology nodes and design rule sets
• Complex mixed-signal connectivity SoC designs
• Automated flow development and optimization

Ready to Drive Connectivity Performance?

Join our team and help optimize the wireless technologies that connect our world.