Physical Design Engineer

Aritrak Technologies; Bengaluru; On-site; INR 900,000 - 1,800,000; Full time

Job summary

Aritrak Technologies is seeking a Physical Design Engineer to perform RTL-to-GDSII physical design flow for ASIC/SoC designs in Bengaluru.

You will work on floorplanning, power planning, placement, CTS, routing, timing closure, and physical verification; analyze and optimize timing, power, and area; handle DRC/LVS checks and ECO flows; and collaborate with synthesis, STA, DFT, RTL and design teams to resolve implementation issues.

Qualifications

• Experience in RTL-to-GDSII physical design flow for ASIC/SoC
• Knowledge of floorplanning, placement, CTS, routing, and physical verification
• Familiar with SDC constraints and timing paths
• Linux/Unix familiarity; Tcl/Python/Perl scripting desirable
• Experience level can range from fresher to senior depending on position

Responsibilities

• Perform RTL-to-GDSII physical design flow for ASIC/SoC designs
• Work on floorplanning, power planning, placement, CTS, routing, and physical verification
• Analyze and optimize timing, power, and area (PPA)
• Perform STA and resolve setup/hold timing violations
• Handle congestion, IR drop, EM, and signal integrity issues
• ECO implementation and timing/area optimization
• Run and debug DRC, LVS, antenna, ERC checks
• Collaborate with synthesis, STA, DFT, RTL, and design teams
• Generate and review GDSII/OASIS, DEF, LEF, SPEF
• Support physical design and tapeout activities

Skills

CMOS/VLSI fundamentals

Timing closure

Power optimization

Physical verification

Linux/Unix

Tcl/Python/Perl scripting

Education

Bachelor's/Master's in Electrical/Electronics/VLSI

Tools

Synopsys ICC2 / Fusion Compiler

Cadence Innovus

Synopsys PrimeTime

StarRC

Calibre

Job description

Physical Design Engineer Job Description

Role: Physical Design / Backend VLSI Engineer

Key Responsibilities

• Perform complete RTL-to-GDSII physical design flow for ASIC/SoC designs.
• Work on floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Analyze and optimize timing, power, area (PPA).
• Perform STA and resolve setup/hold timing violations.
• Handle congestion, IR drop, electromigration (EM), and signal integrity issues.
• Perform ECO implementation and timing/area optimization.
• Run and debug DRC, LVS, antenna, ERC, and other physical verification checks.
• Work with synthesis, STA, DFT, RTL, and custom-design teams to resolve implementation issues.
• Generate and review GDSII/OASIS, DEF, LEF, SPEF, and other implementation data.
• Support block-level and/or full-chip physical design and tapeout activities.

Required Skills

• Strong understanding of CMOS/VLSI physical design fundamentals.
• Good knowledge of:
• Floorplanning
• Placement
• CTS
• Routing
• Timing closure
• Power optimization
• Physical verification
• Hands-on experience with tools such as:
• Synopsys ICC2 / Fusion Compiler
• Cadence Innovus
• Synopsys PrimeTime
• StarRC
• Calibre
• Knowledge of SDC constraints, timing paths, clock definitions, false paths, multicycle paths, etc.
• Understanding of UPF/low-power design is an advantage.
• Scripting knowledge in Tcl, Python, or Perl is highly desirable.
• Familiarity with Linux/Unix environments.

Typical Qualifications

• B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, VLSI, or related fields.
• Experience can range from fresher/entry-level to senior physical design engineer, depending on the position.

Important Interview Topics

For a Physical Design interview, focus especially on:

1. Floorplan and power planning
2. Placement and congestion
3. CTS and clock skew
4. Setup and hold timing
5. Timing optimization
6. Routing and SI/crosstalk
7. IR drop and EM
8. DRC/LVS
9. MMMC/PVT corners
10. ECO flow
11. SDC constraints
12. Physical design Tcl scripting