Senior PD Engineer

Tecquire Solutions; Dadri; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Tecquire Solutions seeks a Digital Physical Design Engineer to drive block-level physical implementation of complex SoCs/ASICs across advanced nodes. You will own key blocks from synthesis to tape-out, ensuring timing, power, area, and signoff quality while collaborating with cross-functional teams and driving flow improvements.

You will execute floorplanning, CTS, routing, STA, and power planning, perform DRC/LVS, and support PDN optimization and DFT integration.

Qualifications

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field.
• 2–6 years of hands-on experience in digital physical design of SoCs or ASICs.
• Proficiency with industry-standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre)

Responsibilities

• Execute physical design activities including floor planning, power planning, placement, CTS, routing, and STA for assigned blocks
• Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoff
• Conduct power integrity analysis (IR drop, EM) and support PDN optimization
• Support DFT implementation and ensure proper test structure integration
• Analyze and debug timing, congestion, power, and signal integrity issues
• Execute ECOs and support tape-out readiness under tight schedules
• Develop and use automation scripts to improve flow efficiency
• Contribute to methodology improvements and standardization efforts
• Collaborate with team members on implementation strategies, constraints, and floorplans

Skills

Independent execution

Structured debugging

Ownership mindset

Clear communication

Education

Bachelors or Masters in Electronics or Electrical Engineering

Tools

Fusion Compiler

Innovus

ICC2

Tempus

PrimeTime

Voltus

RedHawk

Calibre

Job description

We are seeking a strong Digital Physical Design Engineer to drive block-level physical implementation of complex SoCs/ASICs across advanced nodes.

The role involves hands-on execution and ownership of key blocks from synthesis to tape-out, ensuring closure across timing, power, area, and signoff quality, while collaborating with cross-functional teams and contributing to flow improvements.

Responsibilities

• Execute physical design activities including floor planning, power planning, placement, CTS, routing, and STA for assigned blocks
• Perform physical verification (DRC, LVS, Antenna) and resolve violations to achieve clean signoff
• Conduct power integrity analysis (IR drop, EM) and support PDN optimization
• Support DFT implementation and ensure proper test structure integration
• Analyze and debug timing, congestion, power, and signal integrity issues
• Execute ECOs and support tape-out readiness under tight schedules
• Develop and use automation scripts to improve flow efficiency
• Contribute to methodology improvements and standardization efforts
• Collaborate with team members on implementation strategies, constraints, and floorplans

Qualification

• Bachelor’s or Master’s degree in Electronics / Electrical Engineering or related field
• 2–6 years of hands-on experience in digital physical design of SoCs or ASICs
• Proficiency with industry-standard EDA tools (Fusion Compiler / Innovus / ICC2, Tempus / PrimeTime, Voltus / RedHawk, Calibre)
• Solid understanding of:
• Floorplanning and power planning basics
• Placement and routing optimization
• Clock tree synthesis (CTS)
• Static Timing Analysis (STA) and timing closure techniques
• Physical verification and reliability checks
• Exposure to advanced nodes (16nm / 7nm / 5nm preferred)

Soft Skills

• Ability to independently drive and close assigned blocks
• Structured debugging approach for timing, IR/EM, and tool-related issues
• Clear communication of risks and closure status
• Strong ownership mindset and execution discipline