PD Engineer

Quest Global; Bengaluru; On-site; INR 800,000 - 2,000,000; Full time

Job summary

Quest Global is seeking experienced professionals in physical design in Bengaluru, India. Candidates should have a deep understanding of ASIC/SoC design flows and possess hands-on experience in floorplanning, placement, and static timing analysis.

The role demands at least a Bachelor's degree in Electronics/VLSI/Electrical Engineering and 2–10 years of relevant experience. Familiarity with Synopsys and Cadence tools, as well as scripting skills in Tcl/Python, will be advantageous.

Qualifications

• 2–10 years of experience in physical design.
• Hands-on ASICS experience is preferred.
• Experience with advanced nodes (≤16nm) is a plus.

Responsibilities

• Perform floorplanning, placement, clock tree synthesis (CTS), and routing.
• Handle timing closure (STA) including setup and hold fixes.
• Work on power optimization and IR drop analysis.
• Perform physical verification (DRC, LVS, ERC).
• Collaborate with RTL, DFT, and STA teams for design closure.

Skills

ASIC/SoC design flow

Floorplanning & Placement

CTS & Routing

Static Timing Analysis (STA)

Power analysis (IR/EM)

Signal integrity & crosstalk

Scripting (Tcl / Python / Shell)

Education

Bachelor’s or Master’s degree in Electronics / VLSI / Electrical Engineering

Tools

Synopsys Tools (ICC2, PrimeTime, Fusion Compiler)

Cadence Tools (Innovus, Tempus, Voltus)

Mentor Graphics Tools (Calibre DRC/LVS)

Job description

Key Responsibilities

• Perform floorplanning, placement, clock tree synthesis (CTS), and routing
• Handle timing closure (STA) including setup and hold fixes
• Work on power optimization and IR drop analysis
• Perform physical verification (DRC, LVS, ERC)
• Execute ECO implementation and convergence
• Collaborate with RTL, DFT, and STA teams for design closure
• Analyze and fix congestion, signal integrity, and noise issues
• Ensure design meets foundry and sign-off requirements

Required Skills

Technical Skills

• Strong understanding of ASIC/SoC design flow
• Hands‑on experience in:
  • Floorplanning & Placement
  • CTS & Routing
  • Static Timing Analysis (STA)
  • Power analysis (IR/EM)
• Good knowledge of:
  • Process technologies (7nm / 14nm / 28nm etc.)
  • Signal integrity & crosstalk
• Scripting skills:
  • Tcl / Python / Shell

Tools Experience

• Synopsys (ICC2, PrimeTime, Fusion Compiler)
• Cadence (Innovus, Tempus, Voltus)
• Mentor Graphics tools (Calibre DRC/LVS)

Qualifications

• Bachelor’s or Master’s degree in Electronics / VLSI / Electrical Engineering
• 2–10 years of experience in physical design (based on seniority)

Preferred Skills

• Experience in advanced nodes (≤16nm)
• Knowledge of low-power design techniques (UPF/CPF)
• Exposure to DFT and chip-level integration
• Experience in multiple tape‑outs

Key Performance Indicators (KPIs)

• Timing closure (setup/hold violations)
• Power and area optimization
• Design rule clean (DRC/LVS clean)
• On-time project delivery
• Quality of tape‑out