Memory Layout Design Engineer

Broadcom Inc.; Bengaluru; On-site; INR 3,000,000 - 5,500,000; Full time

Job summary

Broadcom Inc. in Bengaluru seeks an experienced Memory/IC Layout Engineer to drive high-quality layouts for submicron FinFET processes. You will apply layout guidelines, lead floor-planning, and ensure timely delivery while coordinating with SOC and library teams.

The role requires deep Cadence proficiency, memory layout expertise, and the ability to train junior engineers in layout methodologies and verification flows.

Qualifications

• 8+ years of experience with a Bachelor's degree or 6+ years with a Master's degree.
• Strong layout knowledge in advanced submicron FinFET processes (TSMC 5nm, 3nm, 2nm).
• Proficiency in Cadence tools for layout, schematic capture, and verification.

Responsibilities

• Understand and apply layout guidelines and new process rules for high-quality layouts.
• Manage scheduling, timelines, and layout floor-planning.
• Ensure end-to-end deliverables are completed with high quality and on time.
• Lead teams, train junior engineers, and document layout methodologies.
• Collaborate with SOC and library teams on integration and design rules.

Education

Bachelor's degree

Master's degree

Tools

Cadence Virtuoso Layout

Layout XL

Cadence Schematic Capture

Calibre

Hercules

VXL/EXL

Job description

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job.2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Job Requirements:Minimum 8+ years of experience with a Bachelor's degree or 6+ years of experience with a Master's degree, strong layout knowledge.Proficiency in using Cadence tools (Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools - Calibre & Hercules).Strong layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14 or Samsung lower FinFET nodes.Key Responsibilities:Understand and apply layout guidelines, new process rules, and technical requirements for high-quality layouts.Manage scheduling, timelines, and layout floor-planning.Ensure end-to-end deliverables are completed with high quality and within the planned schedule.Adapt quickly to new methodologies and communicate effectively with the SOC and library teams.Skill Set(Memory):Proven ability to manage schedules, timelines, and end-to-end deliverables.Experienced in leading teams, training junior engineers, and documenting layout methodologies and guidelines.Proficient in Cadence tools, including Virtuoso Layout, Layout XL, VXL, EXL, and Cadence Schematic Capture.Strong experience in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration) in CMOS processes.Extensive experience with physical verification tools such as Calibre and Hercules (DRC, LVS, ERC, Antenna, and Softcheck Errors).Proficiency in floor-planning, hierarchy layout, and chip integration.Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.Ability to lead teams, train junior engineers, and manage projects effectively.Strong knowledge of memory layout topology; experience with memory compilers is preferred.Knowledge of AI, layout automation, and script/SKILL programming is preferred.Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.Self-reliant with the ability to work both independently and collaboratively.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.