Memory Circuit Design Lead

leadIC Design Pvt Ltd; Dadri; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

leadIC Design Pvt Ltd is seeking an experienced Memory Circuit Design Engineer to join our semiconductor design team and develop advanced memory circuits and macros. You will work on transistor-level design, memory architectures, SPICE simulations and PVT/corner analysis to deliver robust, high-performance memory solutions.

The role requires hands-on experience with SRAM/DRAM/Register File/ROM, memory bitcells, and post-layout verification, collaborating with architecture, layout and

Qualifications

• 8+ years of hands-on experience in Memory Circuit Design / Memory IC Design.
• Strong experience in transistor-level circuit design.
• Strong understanding of CMOS circuit design and semiconductor device fundamentals.
• Hands-on experience with memory technologies: SRAM, DRAM, Register File, ROM.
• Strong understanding of memory architecture and critical memory circuits.
• Experience designing and optimizing bitcells and peripheral circuits.
• Strong hands-on experience with SPICE simulations and circuit-level debugging.
• Experience with Cadence Virtuoso and Spectre or equivalent tools.
• Strong experience with PVT analysis and corner analysis.
• Post-layout simulation and parasitic analysis knowledge.
• Understanding memory timing and performance parameters.
• Experience with power, performance, area and robustness optimization.
• Knowledge of process variation and reliability considerations.

Responsibilities

• Design and develop memory circuits and memory macros at transistor level.
• Work on memory architectures such as SRAM, Register File, ROM and/or DRAM.
• Perform schematic design and transistor-level simulations using SPICE-based tools.
• Analyze memory performance across PVT corners and temperature conditions.
• Optimize memory designs for access time, dynamic power, area and robustness.
• Collaborate with architecture, layout, verification and technology teams.
• Review post-layout simulations and parasitic extraction.
• Support silicon bring-up and post-silicon debug.

Skills

Memory circuit design

Transistor-level circuit design

SPICE simulations

PVT/corner analysis

Memory architectures

Low-power design

Monte Carlo/statistical analysis

Debug circuit-level issues

Python scripting

Education

B.E./B.Tech/M.E./M.Tech in Electronics & Communication, Electrical Engineering, VLSI or related disciplines

Tools

Calibre

PEX / RC extraction tools

Cadence Virtuoso

Spectre

SPICE

Job description

We are looking for an experienced Memory Circuit Design Engineer to join our semiconductor design team and work on the design and development of advanced memory circuits and memory macros.

The ideal candidate will have strong hands-on experience in transistor-level memory circuit design, memory architecture, circuit optimization, SPICE simulation, and PVT/corner analysis. The role will involve working closely with architecture, layout, characterization, verification and physical design teams to deliver robust, high-performance and low-power memory solutions.

Key Responsibilities

• Design and develop memory circuits and memory macros at transistor level.
• Work on memory architectures such as SRAM, Register File, ROM and/or DRAM, depending on project requirements.
• Develop and optimize critical memory circuits including:

Memory bitcells

Address buffers

• Perform schematic design and transistor-level simulations using SPICE-based simulators.
• Analyze memory performance across PVT corners, voltage ranges and temperature conditions.
• Optimize memory designs for:

Access time

Dynamic power

Area

Stability

Yield and robustness

• Perform Monte Carlo and statistical analysis to evaluate process variation and mismatch.
• Analyze memory failure mechanisms including read stability, write ability, leakage, disturb conditions and sense-margin issues.
• Develop and optimize memory circuits for low-voltage and low-power operation.
• Work with layout engineers to ensure robust implementation and minimize layout-dependent effects.
• Review and analyze post-layout simulations, including extracted parasitics.
• Support characterization of memory macros across different PVT conditions.
• Debug circuit-level issues and identify root causes of performance, functionality or yield degradation.
• Collaborate with architecture, layout, verification, characterization and technology teams throughout the design cycle.
• Contribute to design reviews, technical documentation and design methodology improvements.
• Support silicon bring-up, silicon correlation and post-silicon debug, wherever applicable.

Required Skills & Experience

• 8+ years of hands-on experience in Memory Circuit Design / Memory IC Design.
• Strong experience in transistor-level circuit design.
• Strong understanding of CMOS circuit design and semiconductor device fundamentals.
• Hands-on experience with one or more memory technologies:
• SRAM
• DRAM
• Register File
• ROM
• Strong understanding of memory architecture and critical memory circuits.
• Experience designing and optimizing bitcells and peripheral circuits.
• Strong hands-on experience with SPICE simulations and circuit-level debugging.
• Experience with Cadence Virtuoso and Spectre or equivalent tools.
• Strong experience with:
• PVT analysis
• Corner analysis
• Post-layout simulation
• Parasitic analysis
• Understanding of memory timing and performance parameters.
• Experience with circuit optimization for power, performance, area and robustness.
• Strong understanding of process variation, mismatch and reliability considerations.
• Ability to work independently on circuit design problems and drive them to closure.

Preferred / Good-to-Have Skills

• Experience with advanced CMOS/FinFET technology nodes.
• Experience with high-density SRAM or embedded memory macros.
• Experience with high-speed memory design.
• Experience with low-voltage SRAM design.
• Knowledge of:
• SRAM stability
• SNM
• Write Margin
• Read Margin
• Leakage reduction
• Sense amplifier offset
• Experience with DRAM peripheral circuit design, if applicable.
• Experience with memory characterization and Liberty/model generation.
• Familiarity with Calibre DRC/LVS/PEX and post-layout verification.
• Experience working with advanced-node design challenges.
• Scripting knowledge in Python, Perl, Tcl or SKILL is a plus.
• Experience with silicon correlation and post-silicon debug is highly desirable.

Tools

Primary:

Physical Verification / Extraction:

• Calibre
• PEX / RC extraction tools

Simulation / Analysis:

• SPICE
• PVT / Corner Analysis

Scripting:

• Python
• Tcl
• Perl
• SKILL

Education

• B.E./B.Tech/M.E./M.Tech in Electronics & Communication, Electrical Engineering, VLSI or related disciplines.