Senior Lead Engineer - SoC Design Verification

NXP Semiconductors; Maharashtra; On-site; INR 1,400,000 - 2,100,000; Full time

Job summary

NXP Semiconductors in Pune seeks an experienced Senior Design Verification Engineer to lead SoC/IP verification efforts for complex SoCs and security IPs. The role emphasizes ARM-based microcontrollers, low-power verification, and hands-on DV across interfaces in a fast-paced setting.

The candidate will develop verification environments, run simulations, and drive DV closure while mentoring juniors and collaborating with design teams to ensure quality and timely sign-off.

Qualifications

• 5–12 years in SoC/IP verification with participation in tape-outs
• Experience with ARM-based microcontrollers and SoC verification including C-based DV
• Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification
• Familiarity with low-power verification (UPF) and power-aware simulations
• Knowledge of multiple interfaces (SPI, I2C, UART, USB, PCIe, Ethernet, CAN) and security IPs
• Good communication and teamwork in fast-paced environments

Responsibilities

• Develop and own SoC/IP verification suites with coverage goals
• Execute verification according to product specifications and requirements
• Develop, debug and run UVM-based verification environments for RTL/netlist simulation
• Create test cases, stimuli and assertions; run simulations and analyze coverage
• Drive DV closure for diverse IPs and subsystems with maximum coverage and quality
• Collaborate across teams to improve verification flows and reuse
• Mentor junior team members and coordinate with design teams for sign-off

Skills

ARM DV

Verilog/SystemVerilog

UVM

Constrained-Random

EDA Tools

UPF Power

SoC/IP Verification

Interface Protocols

SVA assertions

Education

Bachelor/Master in Microelectronics/ Electronics/ EE

Tools

Synopsys VCS

Cadence Xcelium

Job description

Job Title: Senior Design Verification Engineer / Location: Pune

We are seeking an experienced Design Verification Engineer with 6+ years of expertise for execution of complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low‑power design verification, and experience with multiple interfaces and security IPs. This is a hands‑on role requiring strong technical skills and collaboration in a fast‑paced environment.

Key Responsibilities

• Develop and own SoC‑level and/or IP‑level verification suites with coverage goals.
• Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
• Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.
• Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
• Familiar with both SoC‑level and IP‑level verification environments.
• Collaborate with the team in developing and improving flows for maximum reuse and efficiency.
• Mentor junior team members while actively collaborating with design teams for issue resolution and sign‑off.

Required Qualifications

• Experience: 5-12 years in SoC/IP verification with participation in successful tape‑outs of SoCs.
• Technical Skills:
  • Strong expertise in ARM-based microcontrollers and SoC‑level verification, including C based DV.
  • Proficiency in Verilog, SystemVerilog, UVM, and constrained‑random verification.
  • Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
  • Experience with low‑power verification (UPF) is a plus.
  • Gate‑level simulations and power‑aware simulations is a plus.
  • Good working knowledge of assertions (SVA) and functional coverage.
  • Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI is desirable.
  • Knowledge of Flash memory and security IPs is nice to have.
  • Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage.
• Soft Skills:
  • Comfortable working in a fast‑paced environment.
  • Strong team player with excellent communication skills.
• Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering