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Cadence is seeking a Senior Principal Firmware Engineer to join a dynamic team developing physical layer IPs for high-speed serial-link protocols, applied to Die-2-Die and Chiplet Interconnects. The role requires independence, initiative, and potential project leadership across firmware architecture, implementation, verification, testing, and deployment.
The successful candidate should have strong C programming and embedded firmware skills, experience with microcontrollers, and the ability to
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and healt
The Cadence Advantage
About the Role
Senior Principal Firmware Engineer. This is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols, as applied to Die-2_die and Chiplet Interconnects. The successful candidate will ideally be a highly motivated self-starter who is able to work independently to complete assigned tasks and can also contribute to project leadership. It is expected that the candidate will contribute during all phases of firmware development for high speed Die-2-Die, UCIe IPs from firmware architecture development to implementation, verification, testing and customer deployment.
Responsibilities
Qualifications
Required Skills