Firmware Engineer

Cadence Design Systems India Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,200,000; Full time

Job summary

Cadence Design Systems India Pvt Ltd is seeking a Firmware Engineer II to join the DDR5 PHY Front End Design team. You will develop firmware for DDR5 PHY using microcontrollers, work on bare-metal C, and collaborate with hardware and verification teams to align training algorithms and co-verification plans.

Responsibilities include debugging firmware with RTL simulations, and bringing up on silicon boards. Strong C, scripting, and DDR5 knowledge are required to succeed in this role.

Qualifications

• Experience in bare-metal firmware for high-speed SerDes or memory interface PHYs.
• Strong C programming for embedded software and IDE usage.
• Experience debugging firmware with RTL simulations and silicon bring-up boards.
• Skill with Shell/Perl/Python/TCL scripting.
• Familiarity with DDR5 JEDEC specs and DIMM configurations.

Responsibilities

• Develop firmware for DDR5 PHY using microcontrollers.
• Develop firmware in C with bare-metal programming and low-level APIs.
• Collaborate with hardware designers and memory subsystem architects on training algorithms.
• Collaborate with verification team on firmware-hardware co-verification plan.
• Develop and debug firmware in RTL-based hardware simulations (C + Verilog).
• Develop and debug on Silicon bring-up boards.

Skills

DDR5 knowledge

Bare-metal firmware

C programming

RTL simulations debugging

Shell scripting

Perl scripting

Python scripting

TCL scripting

EDA tool verification

Microcontrollers

Tools

EDA simulators

Waveform viewers

Job description

Firmware Engineer II At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Be part of the Cadence DDR PHY IP Front End Design team responsible for

Job Description

• Develop firmware for DDR5 PHY using microcontrollers
• Developing firmware in C typically involving bare-metal programming and developing low-level APIs on Microcontrollers.
• Responsible for collaborating with hardware designers and memory subsystem architects to derive training algorithms and implement them.
• Responsible for collaborating with the verification team to deduce firmware-hardware co-verification plan.
• Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations)
• Develop and Debug on Silicon bring-up boards.

Required Skills

• Good Knowledge of DDR5 JEDEC spec, knowledge of different DIMM configurations and specifications.
• Relevant experience in developing bare-metal firmware for High-speed SerDes or Memory interface Physical Layer blocks.
• Good Knowledge of C programming language for embedded software development and use of relevant IDE.
• Comfortable debugging RTL simulations involving firmware and microcontroller subsystem.
• Good knowledge of Shell/Perl/Python/TCL scripting
• Good experience on Verification EDA Tools like simulators and waveform viewers

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