Lead/Principal Circuit Design - IO PHY

Cadence; Hyderabad; Hybrid; INR 1,600,000 - 2,600,000; Full time

Job summary

Cadence Hyderabad is seeking a Lead/Principal Circuit Design expert to lead High Speed IO PHY interfaces including PCIe SERDES, DDRIO, HBMIO, UCIe IO, MIPI and USB. The role demands deep circuit design expertise, signal integrity, calibration, and post-silicon qualification across global teams.

You will influence architectures for transmitter/receiver blocks, clocking, and power delivery while coordinating analog macro modeling and layout considerations to ensure robust IO link performance.

Qualifications

• B.Tech / M.Tech degree from prestigious college.
• 6-15 years of strong technical experience in circuit design of High Speed IO PHY Interfaces.
• Strong knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems.
• Working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration, Post-Silicon Qualification of PHY functionality.
• Experience with analog macro modeling and AVM is a plus.

Responsibilities

• Lead the design of High Speed IO PHY Interfaces (PCIe SERDES, DDRIO, MIPI, USB, UCIe).
• Develop architectures for Transmitter/Receiver, Clocking, and Power Delivery blocks.
• Ensure PHY SI analysis, calibration, and post-silicon qualification are performed.
• Oversee design testability and layout impact with reliability considerations (ESD, EMIR).
• Collaborate with global teams and contribute to system-level modelling in Matlab or Verilog tools.

Skills

IO PHY Interfaces

PCIe SERDES

DDRIO PHY

HBM IO

UCIe IO

MIPI

USB

Transmitter Architecture

Receiver Architecture

Clocking Systems

Power Delivery

SI Analysis

System Modelling

Analog Macros

Matlab

Verilog-AMS

Education

B.Tech / M.Tech

Tools

Matlab

Verilog-AMS

Job description

Cadence Hyderabad is Hiring for Lead/Principal Circuit Design - IO PHY

About the Role

The role involves leading the design of High Speed IO PHY Interfaces and requires a strong technical background in circuit design.

Responsibilities

• Education Qualification: B.Tech / M.Tech Degree from prestigious college.
• 6-15 years of strong technical experience in Circuit design of High Speed IO PHY Interfaces like PCIe SERDES, DDRIO PHY, HBMIO, UCIe IO, MIPI, USB etc.
• Strong knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems and blocks is must.
• Must be aware and working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration, Post-Silicon Qualification of PHY functionality, Design and Testability of the IO Link, Power Integrity, Analog Signal Routing Integrity and Signoff etc.
• Should know about lib generation of Analog macros, generating current and timing models of macro blocks.
• Knowledge and work in Real Value Behavioral models of Analog blocks will be a great advantage.
• Experience in System modelling to build High Speed PHY system design / test in Matlab, AMS Verilog or any other tool is required to be considered for Architect position.
• Post-Silicon Testing exposure is desired for Senior designers and Architects.
• All designers should be well aware about layout design requirements and impact, reliability (ESD, EMIR etc) requirements and exposure to Analog models like .libs, Verilog models will be a plus.
• The candidate should have good communication skills and a team player to work in global teams.

Qualifications

B.Tech / M.Tech Degree from prestigious college.

Required Skills

• Strong technical experience in Circuit design of High Speed IO PHY Interfaces.
• Knowledge of architectures and circuits of Transmitter, Receiver, Clocking and Power Delivery Systems.
• Working knowledge of PHY Level Signal Integrity Analysis, Training and Calibration.
• Design and Testability of the IO Link, Power Integrity, Analog Signal Routing Integrity.
• Good communication skills and ability to work in global teams.

Preferred Skills

• Knowledge and work in Real Value Behavioral models of Analog blocks.
• Experience in System modelling to build High Speed PHY system design / test in Matlab, AMS Verilog or any other tool.
• Post-Silicon Testing exposure.