Senior Design Engineer - Analog and Digital Silicon Validation

Cadence Design Systems India Pvt Ltd; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Cadence Design Systems India Pvt Ltd in Bengaluru seeks a Design Engineer II to lead characterization and validation of Analog and Digital IP based Silicon Solutions. You will guide a small team through day-to-day lab tests, isolation of PHY/Controller features, and ensure timely delivery with remote collaboration.

The role requires strong Verilog RTL, Python, and C/C++, plus hands-on lab experience with oscilloscopes and BER testers to validate Ethernet, PCIe, and UCIe interfaces.

Qualifications

• Experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 5-7 years of management experience leading/mentoring a small team of engineers.
• Physical Layer and Protocol layer experience on at least one high speed SERDES (Ethernet/PCIe/UCIe).
• Proficient with lab equipment: oscilloscopes, BER testers, protocol exercisers, analyzers.
• Expert level Verilog RTL coding for FPGA; proficiency in Python and C/C++.

Responsibilities

• Lead/mentor a small team of engineers.
• Coordinate with R&D and Marketing to define scope and deliver results on time.
• Guide day-to-day lab tests and silicon characterization activities.

Skills

Post-Silicon PHY

Systems Interop

Lab Equipment

Verilog RTL

Python

C/C++

Ethernet

PCB Design

Test Automation

Education

BTech

MTech

Tools

Oscilloscopes

Bit Error Rate Testers

Protocol Exercisers

Analyzers

Lab Automation Scripts

Job description

Design Engineer II At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence. Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.

Minimum Qualifications & Professional Experience

• 2-10years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 5-7 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard’s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon. Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize. Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements. Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus. Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures. Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++ We’re doing work that matters. Help us solve what others can’t. Experience Level Senior Level