Sr Design Engineer

NXP Semiconductors NV; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NXP Semiconductors NV in Bengaluru, India, seeks an IO circuit design engineer with 2-4 years in analog/mixed-signal design to work on high-speed interfaces and ESD protection. You will collaborate with cross-functional teams to deliver silicon-ready IP and ensure reliability from design to production.

Role requires hands-on Cadence Virtuoso, SPICE simulators (Spectre/HSPICE/FineSim), and experience with advanced nodes. Prior ownership of complete IO IP development cycle is a plus.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• 2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.
• Strong understanding of CMOS device physics.
• Analog circuit design fundamentals.
• IO architectures and standards.
• ESD design methodologies.
• Hands-on experience in custom circuit design using Cadence Virtuoso.
• Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.
• Experience with advanced technology nodes (16nm/7nm/5nm preferred).
• Good knowledge of LVS, DRC, EMIR, and reliability checks.
• Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.

Responsibilities

• Design and develop custom IO circuits including LVDS, LVCMOS, SSTL, HSTL, DDR interfaces.
• Perform transistor-level design and simulation using advanced CMOS technology nodes.
• Develop and optimize ESD protection circuits including level shifters, input buffers, and output drivers.
• Conduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
• Drive layout reviews and collaborate with physical design teams to ensure design quality and performance targets.
• Support silicon bring-up, characterization, debugging, and production ramp activities.
• Collaborate with system, package, reliability, and product engineering teams.
• Develop and maintain design documentation, specifications, and verification reports.

Skills

CMOS device physics

Analog circuit design fundamentals

IO architectures and standards

ESD design methodologies

Scripting skills

Education

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field

Tools

Cadence Virtuoso

Spectre

HSPICE

FineSim

Job description

Key Responsibilities

Design and develop custom IO circuits including: GPIO

• LVDS
• LVCMOS
• SSTL
• HSTL
• DDR Interfaces
• High-speed SerDes support circuits

Perform transistor-level design and simulation using advanced CMOS technology nodes.

Develop and optimize: ESD protection circuits

• Level shifters
• Input buffers
• Output drivers
• On-chip termination circuits

Conduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.

Perform signal integrity analysis including: IBIS model generation

• Package-aware simulations
• Crosstalk and reflection analysis

Drive layout reviews and work closely with physical design teams to ensure design quality and performance targets.

Support silicon bring-up, characterization, debugging, and production ramp activities.

Collaborate with system, package, reliability, and product engineering teams.

Develop and maintain design documentation, specifications, and verification reports.

Required Qualifications

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.

2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.

Strong understanding of: CMOS device physics

Analog circuit design fundamentals

IO architectures and standards

ESD design methodologies

Hands-on experience in custom circuit design using Cadence Virtuoso.

Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.

Experience with advanced technology nodes (16nm/7nm/5nm preferred).

Good knowledge of LVS, DRC, EMIR, and reliability checks.

Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.

Preferred Skills

Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.

Knowledge of package modeling and SI/PI analysis tools.

Understanding of ESD standards such as HBM, CDM, and IEC.

Experience in silicon validation and lab characterization.

Scripting skills in Python, Perl, Tcl, or SKILL.

Familiarity with IBIS and IBIS-AMI model generation.

Desired Competencies

Strong analytical and debugging skills.

Excellent communication and cross-functional collaboration.

Ability to lead technical discussions and mentor junior engineers.

Proven track record of delivering silicon successfully from specification to production.

Self-driven with strong problem-solving abilities.

Nice to Have

Experience in automotive, AI/ML, networking, mobile, or data center SoCs.

Exposure to functional safety and reliability requirements.

Prior ownership of complete IO IP development cycle.

This role is ideal for an engineer who has hands‑on experience in IO circuit design, ESD, signal integrity, and silicon validation , and is looking to contribute to next‑generation semiconductor products.

More information about NXP in India...