Lead / Manager RTL Design

Keka Technologies Private Limited; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Keka Technologies Private Limited seeks a senior FPGA architect to lead architecture, design, and development of high-speed FPGA systems in Bengaluru. You will own the RTL lifecycle, drive performance trade-offs, and mentor a team of FPGA engineers to deliver robust, Verilog/VHDL designs.

Collaborating with hardware, software, and validation teams, you will integrate PCIe, 10G/25G Ethernet, JESD, and memory interfaces while ensuring lab validation and design documentation standards are met.

Qualifications

• Strong expertise in digital design fundamentals and high-speed FPGA system design.
• Experience with high-speed interfaces: PCIe, 10G/25G Ethernet, JESD, HS DAC/ADC.
• Proven experience in architecting and implementing complex FPGA-based designs.
• Hands-on experience with high-end FPGAs from Intel (Altera), Xilinx (AMD), and Microchip.

Responsibilities

• Lead architecture, design, and development of complex, high-speed FPGA systems.
• Own RTL design lifecycle from specification to validation.
• Provide technical leadership and mentorship to FPGA engineers.
• Drive system architecture decisions and design trade-offs for performance, power, and cost.
• Collaborate with hardware, software, systems, and validation teams to define requirements and verification strategies.
• Integrate and optimize high-speed IPs (PCIe, 10G/25G Ethernet, JESD, GT/MAC, memory interfaces).
• Lead design verification planning including testbench development, simulation, and hardware validation.
• Oversee board bring-up, debugging, and performance tuning with lab equipment.
• Interface with DRDO labs and other defense/research organizations for project execution.
• Ensure documentation, coding standards, and design processes across projects.

Skills

Digital design

FPGA system design

PCIe

10G/25G Ethernet

JESD

VHDL/Verilog

FPGA toolchains

Lab debugging

Leadership

Stakeholder management

Tools

Vivado

Quartus

Libero

Job description

Lead the architecture, design, and development of complex, high-speed digital systems using FPGAs.

Own end-to-end RTL design lifecycle (specification, design, coding, simulation, synthesis, timing closure, and validation).

Provide technical leadership and mentorship to a team of FPGA engineers; review designs and enforce best practices.

Drive system architecture decisions, interface definitions, and design trade-offs for performance, power, and cost.

Collaborate with cross-functional teams (hardware, software, systems, validation) to define requirements and verification strategies.

Integrate and optimize high-speed IPs such as PCIe, 10G/25G Ethernet, JESD, GT/MAC, and memory interfaces.

Lead design verification planning, including testbench development, simulation, and hardware validation.

Oversee board bring‑up, debugging, and performance tuning using lab equipment.

Identify and resolve complex issues during development, testing, and field deployment.

Ensure documentation, coding standards, and design processes are followed across projects.

Interface with external stakeholders (including labs such as DRDO) for project execution and technical alignment.

Required Skills:

• Strong expertise in digital design fundamentals and high-speed FPGA system design.
• Extensive experience with high-speed interfaces: PCIe, 10G/25G Ethernet, JESD, HS DAC/ADC.
• Proven experience in architecting and implementing complex FPGA-based designs.
• Hands‑on experience with high‑end FPGAs from Altera (Intel), AMD (Xilinx), and Microchip.
• Experience working on projects with DRDO labs or similar defense/research organizations.
• Strong electronics fundamentals and system-level understanding.
• Expertise in timing closure, CDC, constraints, and performance optimization.
• Strong debugging skills using lab equipment (Oscilloscope, Logic Analyzer, DMM).
• Excellent leadership, communication, and stakeholder management skills.

Preferred Skills:

• Proficiency in VHDL, Verilog/SystemVerilog, Python, and TCL scripting.
• Experience with PCIe, 10G/25G Ethernet, AXI-4, and high-speed transceivers.
• Exposure to verification methodologies (UVM/advanced simulation environments).
• Experience with FPGA toolchains (Vivado, Quartus, Libero) and CI/CD flows.
• Knowledge of embedded processors (SoC FPGAs) and firmware/software integration.