Fpga Developer

American Megatrends; Kolkata District; On-site; INR 1,300,000 - 1,900,000; Full time

Job summary

American Megatrends is seeking a seasoned FPGA/RTL engineer to research architectures, design RTL modules, and prototype acceleration frameworks. You will develop PoCs to evaluate performance and tradeoffs while exploring modern FPGA toolchains and HLS methods.

You will collaborate with RTL and firmware teams to debug, verify, and optimize complex IP blocks, using UVM benches and signal-tap tools across Linux/Windows environments.

Qualifications

• Hands-on FPGA/RTL design and development experience.
• Strong command of VHDL or Verilog/SystemVerilog for RTL.
• Experience with PCIe, Ethernet, TCP/IP, Packet processing, USB, etc.
• Ability to analyze and isolate RTL and test bench issues.
• Proficient with UVM testbenches and Linux/Windows environments.
• Solid understanding of digital design concepts, algorithms and trade-offs.
• Experience in developing small IP blocks from scratch and basic verification.
• Familiarity with SPI, I2C, UART and AXI protocols.

Responsibilities

• Conduct research and feasibility studies on FPGA architectures, FPGACPU/GPU codesign, and acceleration frameworks.
• Architect and prototype RTL modules, pipelines, and hardware algorithms.
• Develop PoC implementations to evaluate performance, latency, throughput, and tradeoffs.
• Explore FPGA toolchains, HLS methods, and hardware optimization techniques.
• Perform profiling, benchmarking, and architectural exploration across FPGA platforms.
• Document findings and design trade-offs for internal teams.
• Estimate new features, debug test failures, and resolve RTL issues with RTL/firmware engineers.

Skills

FPGA/RTL design

VHDL/Verilog/SystemVerilog

PCIe/Ethernet/USB/packet processing

RTL debugging and testbenches

UVM testbenches

ILA/SignalTap debugging

Linux/Windows environments

digital design concepts

IP blocks development

AXI/SPI/I2C/UART protocols

HLS for acceleration

SoC FPGA platforms exposure

Python/MATLAB scripting

Tools

UVM

ILA/SignalTap

Job description

Role & responsibilities

• Conduct research and feasibility studies on FPGA architectures, FPGACPU/GPU codesign, and acceleration frameworks.
• Architect and prototype novel RTL modules, pipelines, and hardware algorithms.
• Develop proofofconcept (PoC) implementations to evaluate performance, latency, throughput, and resource tradeoffs.
• Explore emerging FPGA toolchains, HLS methods, and hardware optimization techniques.
• Perform profiling, benchmarking, and architectural exploration across FPGA platforms.
• Document findings, design trade-offs, and research insights for internal teams.
• Estimation of new features, Debug test failures to determine the root cause; work with other RTL and firmware engineers to resolve any issues.

Skill Requirements:

Mandatory skills:

• Handson experience in FPGA/RTL design and development
• Strong command of VHDL or Verilog/SystemVerilog for RTL development.
• Experience in developing RTL designs in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc.
• Excellent ability to analyse and isolate RTL and test bench issues
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Strong background in simulation, verification, and debugging using ILA/SignalTap.
• Solid understanding of digital design concepts, algorithms, and architectural trade-offs.
• Should be able to develop the small blocks of IP from scratch and do basic functional verification.
• Should be familiar with protocols like SPI, I2C, UART and AXI.

Desirable Skills:

• Experience with High-Level Synthesis (HLS) for algorithm acceleration.
• Exposure to SoC-based FPGA platforms (Zynq/Ultrascale+/Stratix 10/Agilex).
• Scripting for experimentation: Python, MATLAB, Tcl, Bash.
• Understanding of PCIe, Ethernet, DDR, or high-speed I/O interfaces.