FPGA Lead

Cortex Consultants LLC; Bengaluru Urban; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

Cortex Consultants LLC is seeking a highly skilled RTL Design Engineer in Bengaluru Urban, Karnataka. The role focuses on designing Register-Transfer Level (RTL) Intellectual Property, particularly for low latency video connectivity systems. Ideal candidates should have 8-15 years of experience, strong knowledge of AMD-Xilinx FPGA Architecture, and proficiency with various IP protocols.

This position requires excellent collaboration skills and hands-on expertise in Verilog/System Verilog coding, as well as familiarity with tools like Vivado. A commitment to learning and adapting to new technologies is essential.

Qualifications

• 8-15 years of experience in FPGA and video domain designs.
• Proven experience with various IP protocols at the IP level.
• Strong understanding of resource optimization and timing flows.

Responsibilities

• Design Register-Transfer Level (RTL) Intellectual Property with a focus on video connectivity.
• Participate in design, architecture, documentation, and implementation of systems.
• Collaborate with different teams across various time zones.

Skills

Video domain IPs / Digital IPs

MIPI CSI / MIPI DSI / DisplayPort / HDMI / SDI

AMD/Xilinx FPGA device and Vivado toolchain

Synthesizable Verilog/ System Verilog RTL coding

Lint, CDC, synthesis flow

TCL, Perl, Python

SERDES architecture

Strong communication and presentation skills

Job description

Job Overview

We are seeking a highly skilled and experienced RTL Design Engineer with a strong knowledge of AMD-Xilinx FPGA Architecture. In this role, you will design Register-Transfer Level (RTL) Intellectual Property (IP) with a focus on video connectivity subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the low latency video connectivity systems. Additionally, you will be responsible for RTL coding of blocks specified by you or others, and for various front-end methodology flows that include resource optimization, clock domain crossing and reset domain crossing.

Role Details

FPGA Lead

Experience: 8-15 years

Notice Period: Immediate to 30 Days

Work Mode: 5 Days office

Qualifications

• Must have proven experience working on Video domain IPs / Digital IPs.
• Must have proven experience working on one or more protocols at the IP level: MIPI CSI / MIPI DSI / DisplayPort / HDMI / SDI.
• Hands on experience with AMD/Xilinx FPGA device and Vivado toolchain.
• Hands on experience with architecting / micro-architecture / detailed design from functional specifications.
• Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for FPGA designs.
• Lint, CDC, synthesis flow and static timing flows, formal checking, etc. experience.
• Working knowledge / experience in TCL, Perl, Python is an added advantage.
• SERDES architecture knowledge is a plus.
• Has a solid desire to learn and explore new technologies.
• Strong communication and presentation skills.
• Close collaboration with different teams across various time zones.