FPGA RTL Design Engineer

UST; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

UST is seeking an experienced FPGA RTL Design Engineer to join our high-performance hardware team in Bengaluru, India. The role focuses on RTL design, verification, and bring-up for FPGA-based SoC/FPGA platforms.

You will design RTL in Verilog/SystemVerilog, run synthesis and timing closure, develop testbenches, and collaborate with hardware, firmware, and system teams to ensure robust integration and validation.

Qualifications

• 4+ years of experience in FPGA RTL design and verification.
• Proficient in Verilog/SystemVerilog and digital design.
• Experience with FPGA tools such as Xilinx Vivado or Intel Quartus.
• Strong timing analysis and CDC understanding.
• Experience with simulation and debugging tools (ModelSim, Questa, VCS).
• Familiarity with interfaces such as PCIe, Ethernet, DDR, AXI, SPI, I2C, UART.
• Excellent problem-solving and debugging skills.

Responsibilities

• Design RTL using Verilog/SystemVerilog for FPGA-based applications.
• Perform synthesis, place & route, timing closure, and performance optimization.
• Develop and execute functional verification plans, testbenches, and debugging activities.
• Collaborate with hardware, firmware, and system teams for integration and validation.
• Analyze and resolve design, timing, and FPGA implementation issues.
• Support board bring-up, lab validation, and customer issue resolution.

Skills

FPGA RTL design

Verification

Verilog/SystemVerilog

Digital design

Timing closure

CDC

Reset synchronization

Simulation tools

Interfaces (PCIe/AXI/DDR)

Tools

Xilinx Vivado

Intel Quartus

Job description

We are seeking a skilled FPGA RTL Design Engineer with 4+ years of experience in FPGA development and digital design. The candidate will be responsible for RTL design, implementation, verification, and FPGA bring-up for high-performance SoC/FPGA-based solutions.

Key Responsibilities:

• Design and develop RTL using Verilog/SystemVerilog/VHDL for FPGA-based applications.
• Perform FPGA synthesis, place & route, timing closure, and performance optimization.
• Develop and execute functional verification plans, testbenches, and debugging activities.
• Collaborate with hardware, firmware, and system teams for integration and validation.
• Analyze and resolve design, timing, and FPGA implementation issues.
• Support board bring-up, lab validation, and customer issue resolution.

Required Skills:

• 4+ years of experience in FPGA RTL design and verification.
• Strong proficiency in Verilog/SystemVerilog and digital design fundamentals.
• Experience with FPGA tools such as Xilinx Vivado, Intel Quartus, or equivalent.
• Good understanding of timing analysis, CDC, reset synchronization, and FPGA architectures.
• Experience with simulation and debugging tools (ModelSim, Questa, VCS, etc.).
• Familiarity with interfaces such as PCIe, Ethernet, DDR, AXI, SPI, I2C, or UART.
• Strong problem-solving and debugging skills.