Senior Design Verification Engineer

ACL Digital; Bengaluru; Hybrid; INR 2,500,000 - 4,200,000; Full time

Job summary

A dynamic IT services firm is looking for a Senior Verification Engineer to join their team in Bangalore. This role involves hands-on experience with UVM RAL and strong expertise in SoC-level verification and Gate-Level Simulation. Candidates with 5–8 years of experience are preferred. The position offers a hybrid work model and the company is committed to diversity and inclusivity.

Qualifications

• Hands-on experience with UVM RAL.
• Experience with Gate-Level Simulation (GLS).
• Power-aware simulation experience.
• Expertise in Register Access Tests.
• Good understanding of Register Maps.
• Proficient in RAL methods.
• Ability to debug and verify SoC integration scenarios.
• 5–8 years of experience in relevant field.

Responsibilities

• Hands-on experience with UVM RAL – Register Abstraction Layer.
• Strong in SoC-level verification and Gate-Level Simulation (GLS).
• Power-aware simulation experience is a must.
• Expertise in Register Access Tests – Backdoor, POR, Reg Write/Read.
• Good understanding of Register Maps and RAL Integration flow.
• Proficient in RAL methods – write, read, peek, poke.
• Ability to debug and verify SoC integration scenarios effectively.

Skills

Hands-on experience with UVM RAL

Experience with Gate-Level Simulation (GLS)

Power-aware simulation experience

Expertise in Register Access Tests

Good understanding of Register Maps

Proficient in RAL methods

Ability to debug and verify SoC integration scenarios

Education

5–8 years of experience in relevant field

Job description

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Senior Executive Talent Acquisition | Hiring Skilled VLSI Talents | ASIC RTL, DV, DFT, Physical Design, STA, Post Silicon Validation Engineers

About the Company

Be part of a dynamic verification team working on next-gen SoC designs with exposure to complex verification flows and client interaction.

About the Role

We are looking for a Senior Verification Engineer (SoC / UVM RAL / GLS) to join our team in Bangalore (Hybrid) with 5–8 years of experience. Immediate joiners are preferred.

Responsibilities

• Hands-on experience with UVM RAL – Register Abstraction Layer.
• Strong in SoC-level verification and Gate-Level Simulation (GLS).
• Power-aware simulation experience is a must.
• Expertise in Register Access Tests – Backdoor, POR, Reg Write/Read.
• Good understanding of Register Maps and RAL Integration flow.
• Proficient in RAL methods – write, read, peek, poke.
• Ability to debug and verify SoC integration scenarios effectively.

Qualifications

• Education details: 5–8 Years of experience in relevant field.

Required Skills

• Hands-on experience with UVM RAL.
• Experience with Gate-Level Simulation (GLS).
• Power-aware simulation experience.
• Expertise in Register Access Tests.
• Good understanding of Register Maps.
• Proficient in RAL methods.
• Ability to debug and verify SoC integration scenarios.

Preferred Skills

• Experience with complex verification flows.

Pay range and compensation package

• Pay range or salary or compensation details not specified.

Equal Opportunity Statement

We are committed to diversity and inclusivity in our hiring practices.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Industries

• IT Services and IT Consulting
• Semiconductor Manufacturing

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