DV Lead

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 2,000,000 - 4,200,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd is seeking a Senior/Lead ASIC Verification Engineer in Bengaluru to lead a verification team and drive IP/SOC verification programs. Expertise in SystemVerilog, UVM and C is essential, with hands-on experience in front-end verification tools.

Knowledge of Ethernet/PCIe, Chi protocol, and scripting (Python/Perl/shell) is highly valued, along with debugging and analytical skills. Desirable: power-aware, GLS, and formal verification.

Qualifications

• Experience in verification of IP/SOC.
• Hands-on experience in Front-end verification tools.
• Desirable knowledge of Power aware verification, GLS, Formal Verification.

Responsibilities

• Able to Lead and motivate the team within tight schedules.
• Verify ASIC design, architecture and microarchitecture using advanced methodologies.
• Define verification scope, develop infrastructure and verify correctness.

Skills

SystemVerilog

UVM

C

Ethernet

PCIe

Chi protocol

Debugging

Analytical skills

Python scripting

Perl scripting

Shell scripting

Front-end verification

Power aware verification

GLS

Formal Verification

Tools

Front-end verification tools

Job description

Looking for an Senior/Lead ASIC Verification Engineer

experience in verification of IP/SOC.

• Must have experience in System Verilog, UVM, C.
• Ethernet/PCIe/Chi protocol knowledge
• Should have good debugging and analytical skills.
• Good to have Scripting knowledge (Python/Perl/shell).
• Hands-on experience in Front-end verification tools.
• Desirable to have knowledge of Power aware verification, GLS, Formal Verification.

Roles And Responsibilities

• Able to Lead and motivate the team within the constraints of tight schedules.
• Responsible for verifying the ASIC design, architecture and microarchitecture using advanced verification methodologies.
• You are expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.