Lead Engineer - Design Verification (Low power UPF/CPF)

Silicon Labs; Hyderabad; On-site; INR 2,500,000 - 4,500,000; Full time

Benefits offered by this job

Equity Rewards (RSUs)

Insurance plans with Outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs in Hyderabad, India, seeks an experienced Design Verification engineer focused on low-power verification for complex SoCs. You will validate power intent with UPF/CPF, develop test plans for low-power modes, and own end-to-end DV, including testbench and coverage closure.

The role requires 6–8 years in design verification, strong SystemVerilog/UVM skills, and knowledge of low-power SoC constructs. Collaboration across RTL, architecture, and physical teams is essential.

Qualifications

• BS/MS in Electrical or Computer Engineering (or related field).
• 6–8 years of experience in design verification.
• Strong SystemVerilog/UVM skills.
• Experience with assertion-based and coverage-driven verification.
• Solid understanding of low-power design techniques.
• Experience with UPF/CPF-based verification.
• Knowledge of low-power SoC constructs (clock gating, isolation, level shifters, retention).
• Strong debugging and problem-solving skills.

Responsibilities

• Understand and verify power domains and power intent (UPF/CPF).
• Develop and execute test plans for low-power modes and states.
• Own end-to-end DV: testbench development, testcases, assertions, debugging (RTL/UPF).
• Drive functional and assertion coverage closure.
• Build and enhance SystemVerilog/UVM verification environments.
• Perform power-aware verification and debug complex issues.
• Collaborate with cross-functional teams and explore advanced DV methodologies.

Skills

SystemVerilog/UVM

Assertion-based verification

Coverage-driven verification

Low-power design techniques

UPF/CPF verification

Low-power SoC constructs

Debugging and problem-solving

Education

BS/MS in Electrical or Computer Engineering

Tools

Synopsys NLP tools

Python/Perl scripting

ASIC tools and flows

Job description

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

The Role :

In this role, you will work on low-power design verification for complex SoCs, ensuring robust and power-efficient silicon. You will focus on validating power intent and low-power features using UPF/CPF methodologies across the design lifecycle.

Meet the Team :

The Design Verification team collaborates closely with RTL, architecture, and physical design teams to deliver high-quality silicon. We focus on coverage-driven verification and advanced low-power methodologies.

Responsibilities :

• Understand and verify power domains and power intent (UPF/CPF)
• Develop and execute test plans for low-power modes and states
• Own end-to-end DV: testbench development, testcases, assertions, debugging (RTL/UPF)
• Drive functional and assertion coverage closure
• Build and enhance SystemVerilog/UVM verification environments
• Perform power-aware verification and debug complex issues
• Collaborate with cross-functional teams and explore advanced DV methodologies

Requirement :

Minimum Qualifications:

• BS/MS in Electrical or Computer Engineering (or related field)
• 6–8 years of experience in design verification
• Strong SystemVerilog/UVM skills
• Experience with assertion-based and coverage-driven verification
• Solid understanding of low-power design techniques
• Experience with UPF/CPF-based verification
• Knowledge of low-power SoC constructs (clock gating, isolation, level shifters, retention)
• Strong debugging and problem-solving skills

Nice to Have:

• Experience with formal/static verification
• Familiarity with Synopsys NLP tools
• Knowledge of GLS / PA-GLS
• Scripting skills (Python/Perl)
• Experience with ASIC tools and flows

Why Join Silicon Labs :

• Work on cutting-edge low-power SoC designs
• Solve complex challenges in power-aware verification
• Collaborate across design and verification teams
• Grow your expertise in advanced DV methodologies

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Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making"

Benefits & Perks :

• Equity Rewards (RSUs)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.