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Silicon Labs is seeking a senior VLSI verification engineer in Hyderabad to lead AMS verification for mixed-signal SOCs/IPs. You will own testbench development, regression suites, and collaboration across design, SoC, and PD teams.
Required are 10–15 years of industry experience, strong Verilog, SystemVerilog, Verilog-AMS skills, and familiarity with Cadence/Synopsys/Mentor toolchains. The role demands leadership and clear communication within a multi-site environment.
Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
The position involves design verification of next generation IP's /SoC's with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS.
Candidate will require close interactions with Design, SoC, Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification.
10-15 years in Industry
Bachelor or Master's degree in Electrical and/or Computer Engineering
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
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