Lead Engineer

Angel and Genie; Bengaluru; On-site; INR 2,400,000 - 5,200,000; Full time

Job summary

Angel and Genie is seeking a senior DFT Architect to own the DFT strategy for complex SoCs. You will lead RTL integration, scan insertion, and test architecture, coordinating with RTL, STA, and PD teams to deliver robust DFT solutions.

The role requires 12+ years in DFT, hands-on experience with MBIST, BISR, JTAG, and constraint-aware design, plus proficiency with Synopsys DFT tools. You will mentor engineers, drive automation, and sign off on tapeout readiness across multiple programs.

Qualifications

• 12+ years of experience in DFT architecture and implementation for complex SoCs.
• Proven track record of leading DFT implementation and signoff on multiple projects.
• Strong expertise in: Scan, Compression, and ATPG methodologies.
• Experience with MBIST, BISR, and memory repair.
• Knowledge of JTAG / TAP and Boundary Scan.
• Hands-on experience with DFT tools like Synopsys DFTMAX/TestMAX and SpyGlass DFT.

Responsibilities

• Lead DFT RTL integration, scan insertion, and test architecture implementation.
• Define and drive DFT plans across multiple concurrent SoC programs.
• Act as the technical authority and signoff owner for all DFT-related decisions.
• Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and implementation.
• Drive ATPG pattern generation, simulation, and debug to ensure high test coverage and quality.
• Interface with manufacturing, ATE, and OSAT teams on test requirements and vector delivery.

Skills

DFT architecture

RTl integration

ATPG

MBIST

BISR

JTAG/TAP

Boundary Scan

Leadership

Automation

Education

B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering

Tools

Synopsys DFTMAX / TestMAX

SpyGlass DFT

Job description

• Tessent based SSN insertion at block or Top level
• SSN validation
• Responsible for Implementing and integrating scan insertion, scan compression, MBIST, OCC and boundary scan at gate/RTL level.
• Team Handling Skill is preferred.

Key Responsibilities

• Own SoC-level DFT architecture and strategy for custom and platform-based
• SoCs.
• Define and drive DFT implementation plans across multiple concurrent SoC
• programs.
• Act as the technical authority and signoff owner for all DFT-related decisions and

Execution & Technical Ownership

• Lead DFT RTL integration, scan insertion, and test architecture implementation.
• Own and drive:
• Scan, Compression, and ATPG strategy
• MBIST, BISR, and redundancy implementation
• JTAG / TAP, Boundary Scan, and debug infrastructure
• Ensure DFT readiness across functional, scan, and low-power modes.
• Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and
• implementation.
• Drive ATPG pattern generation, simulation, and debug to ensure high test
• coverage and quality.

Cross-Functional & Manufacturing Interface

• Work closely with physical design teams to ensure scan and test logic closure
• with minimal PPA impact.
• Interface with manufacturing, ATE, and OSAT teams on test requirements, vector
• delivery, and silicon bring-up.
• Support post-silicon debug, yield ramp, and test optimization.
• Represent in customer-facing technical discussions related to DFT
• strategy and signoff.
• Define and standardize DFT methodologies, flows, and checklists across
• programs.
• Drive automation, scripting, and reuse to improve DFT efficiency and
• Mentor and develop DFT engineers and leads, building deep technical and
• Review and approve DFT signoff reports and tapeout readiness criteria.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.
• 12+ years of experience in DFT architecture and implementation for complex
• SoCs.
• Proven track record of leading DFT implementation and signoff on multiple
• Strong expertise in:
• Scan, Compression, and ATPG methodologies
• MBIST, BISR, and memory repair schemes
• JTAG / TAP and Boundary Scan
• DFT RTL integration and pattern simulation
• Hands-on experience with industry-standard DFT tools, such as:
• Synopsys DFTMAX / TestMAX
• SpyGlass DFT (or equivalent)
• Strong understanding of:
• Scan and test-mode timing closure
• Physical implementation constraints for DFT
• Experience working with manufacturing, ATE, and post-silicon validation teams.
• Excellent problem-solving, communication, and leadership skills.