Engineer - ASIC Verification

MosChip Technologies Limited; Bengaluru; On-site; INR 600,000 - 900,000; Full time

Job summary

MosChip Technologies Limited is seeking a verification engineer to develop and maintain verification environments for chip and module level designs. You will use SystemVerilog, UVM, and C/C++ to create scalable testbenches, write tests, and automate regressions.

You will define verification plans with architects and designers, implement coverage, assertions, and debug techniques, and collaborate across teams to ensure robust tapeout readiness in a fast-paced setting.

Qualifications

• Develop verification testbench components at chip/module level using SystemVerilog and C/C++.
• Use verification methodologies (UVM, OO) to develop extendable test-bench environments.
• Define and execute detailed verification plan from spec with architects, designers and system engineers.
• Write tests, debug tests, automate regression scripts and regression environment.
• Incorporate code-coverage, functional coverage, assertions, cover-groups to achieve verification completeness prior to tapeout.
• Organized and creative thinker with ability to multitask and interface with different teams.

Responsibilities

• Develop verification testbench components at chip/module level using SystemVerilog and C/C++.
• Use verification methodologies (OO, UVM) to build extendable test-bench/test-cases environment.
• Define and execute detailed verification plan from spec working with architects, designers, system engineers.
• Write tests, debug tests, automate regression scripts and regression environment.
• Incorporate code-coverage, functional coverage, assertions, cover-groups to achieve 100% verification completeness prior to tapeout.
• Organized and creative thinker, motivated and independent learner who can multitask in a dynamic environment.

Skills

Attention to detail

Communication skills

Multitasking

Independent learner

Team collaboration

Tools

SystemVerilog/Verilog

UVM

C/C++

ncVerilog (Incisive)

VCS

Eldo

Verdi

Debussy

Perl

Tcl/Tk

Shell

Job description

• Develop verification testbench components for chip/module level using System Verilog, C/C++.
• Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment.
• Define and execute detailed verification plan from spec working with architects, designers, system engineers.
• Write tests, Debug tests, automate regression scripts and regression environment.
• Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
• Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.
• Excellent debugging skills in both SW and ASIC hardware.
• Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc.
• Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
• Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy.
• Good understanding of latest formal verification techniques, assertions, properties is a plus.
• Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus.
• Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus.
• Good written and oral communication skills. Ability to clearly document plans.
• ability to interface with different teams and prioritize work based on project needs.