Lead and Senior Physical Design Engineer

Pronesis Technologies; Ahmedabad District; On-site; INR 1,800,000 - 3,600,000; Full time

Job summary

Pronesis Technologies in Ahmedabad/Bengaluru is seeking Lead and Senior Physical Design Engineers to drive end-to-end physical design flows for complex ASIC/SoC projects. You will work with RTL, logic, and circuit teams to meet timing, power, and area goals, and mentor junior engineers throughout tape-out activities.

The role requires strong hands-on experience with DRC/LVS, clock-tree synthesis, and industry-standard EDA tools.

Qualifications

• Strong expertise in physical design including flow steps and timing closure.
• Hands-on experience with DRC/LVS and reliability checks.
• Solid understanding of logic and circuit design principles.
• Proficiency in RTL design concepts and flows.
• Experience with EDA tools and flow automation scripting.
• Strong analytical, problem-solving and debugging skills.
• Ability to lead and mentor teams and manage deliverables.
• Bachelor's or Master's degree in Electrical/Electronics with ASIC/SoC experience.

Responsibilities

• Drive physical design flows: floorplanning, placement, routing, clock tree synthesis, timing closure.
• Collaborate with RTL, logic, and circuit design teams throughout the project.
• Perform physical verification (DRC/LVS) and optimize power, performance, area.
• Support tape-out and design sign-off; review junior engineers and improve methods.
• Engage in technical discussions with global clients and provide status updates.
• Contribute to design methodology improvements and best practices.

Skills

Physical design expert

Physical verification

Logic & circuit design

RTL design concepts

EDA tools

Automation scripting

Leadership & mentoring

Education

Bachelor's or Master's in Electrical Engineering / Electronics

Tools

Cadence

Synopsys

Mentor Graphics

Job description

Company Description:
Pronesis Technologies is a global engineering services company founded by industry veterans with a focus on delivering high-quality, timely solutions for leading technology organizations. The company partners with clients worldwide to provide specialized expertise in ASIC/VLSI design, SoC verification, physical design, and verification IP development. Pronesis also offers services in embedded product development, including hardware design and testing, and firmware/embedded software development. In addition, the company supports end-to-end product engineering, from implementation and roll-out to testing, support, and certification, creating a comprehensive environment for technical professionals to grow their careers.
Role Description:
The Lead and Senior Physical Design Engineer role is a full-time with minimum experience of 3 years, on-site position based in Ahmedabad and Bengaluru. The person in this role will drive and execute physical design flows, including floorplanning, place-and-route, clock tree synthesis, and timing closure for complex ASIC/SoC projects. Day-to-day responsibilities include collaborating with RTL, logic, and circuit design teams, performing physical verification (DRC/LVS), optimizing power, performance, and area, and ensuring design signoff using industry-standard EDA tools. The role involves reviewing and guiding junior engineers, defining best practices, contributing to methodology improvements, and supporting tape-out activities. The engineer will also participate in technical discussions with global clients, provide status updates, and help resolve design and implementation issues throughout the project lifecycle.
Qualifications

• Strong expertise in Physical Design, including floorplanning, placement, routing, clock tree synthesis, and timing closure.
• Hands-on experience with Physical Verification, such as DRC, LVS, and reliability checks using industry-standard tools.
• Solid understanding of Logic Design and Circuit Design principles, including combinational and sequential logic and basic analog/digital interface concepts.
• Proficiency in RTL Design concepts and flows, with the ability to collaborate effectively with RTL and front-end design teams.
• Experience with EDA tools (e.g., Cadence, Synopsys, Mentor) and familiarity with scripting languages such as TCL, Python, or Perl for flow automation.
• Strong analytical, problem-solving, and debugging skills, with attention to detail in timing, power, and area optimization.
• Ability to lead and mentor engineering teams, communicate clearly with cross-functional and client teams, and manage project deliverables.
• Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field, with several years of relevant industry experience in ASIC/SoC physical design.