Lead Analog Validation Engineer

Cadence; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Cadence Bangalore is seeking an experienced Systems Validation engineer to lead pre- and post-silicon prototyping, validation and hardware design for high-speed SERDES test chips. You will drive system-level validation across PCIe, CXL, UCIe and Ethernet with cross-functional teams.

Role requires hands-on lab skills, FPGA/SoC experience and the ability to mentor junior engineers while guiding bring-up, debugging and compliance activities through release.

Qualifications

• 5-15 years (with Btech) or 3 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 2-3 years of management experience leading/mentoring a small team of engineers.
• Physical Layer and Protocol layer experience on at least one high-speed SERDES on PCIe/CXL/UCIe/Ethernet.

Responsibilities

• Pre Silicon emulation and Verification of System in NCSIM/Palladium/other simulators.
• Hardware and Subsystem Board Design for all Projects. (HW/SW infrastructure designed within team)
• Prototyping and Firmware Development for High Speed Serdes (PCIe, CXL, UCIe, USB, ethernet).
• Lead the Bring up, Debug, Compliance efforts and System level Characterization to report release.
• Engage in interop and Customer Debug.

Skills

System testing

PCIe

UCIe

Verilog RTL

Python

C/C++

Lab equipment

Education

B.Tech

M.Tech

Tools

Oscilloscopes

Bit Error Rate Testers

Protocol Exercisers

Analyzers

Job description

Cadence Bangalore is Hiring for Analog electrical and System Validation.

About the Role

The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips.

Responsibilities

• Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators.
• Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team)
• Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL, UCIe, USB, ethernet.
• Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release.
• Engage in interop and Customer Debug.

Qualifications

• Minimum Qualifications:
• 5-15 years (with Btech) or 3 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 2-3 years of management experience leading/mentoring a small team of engineers.
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet.
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.

Required Skills

• Experience leading System testing efforts for SERDES solutions.
• Experience in PCIe/UCIe LTSSM states is a plus.
• 1-2 years of experience in FPGA Design and Schematic design.
• 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus.
• Familiarity with Verilog RTL coding for FPGA, python, C/C++.

Preferred Skills

Seasoned Systems Validation engineer who can lead SERDES projects (PCIe/CXL/UCIe) and mentor Juniors.

Pay range and compensation package

Refer to Cadence Website for more details on our SERDES IP's.