Senior FPGA Design Engineer

Altera Corporation; Bengaluru; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Altera Corporation in Bengaluru seeks an experienced FPGA Design Engineer to develop FPGA-based solutions for pre-silicon validation and hardware prototyping. You will implement RTL in Verilog, integrate high-speed interfaces, and optimize timing with CDC awareness.

The role requires 6+ years in FPGA design, strong Verilog/SystemVerilog skills, and experience with PCIe, DDR, Ethernet, and LPDDR memory interfaces.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 6+ years FPGA design and implementation experience.
• Strong proficiency in Verilog/SystemVerilog and digital logic design.
• Experience with Altera Quartus Prime Pro development environments.
• Experience with FPGA synthesis, timing closure, and implementation.
• Strong understanding of clock domain crossing (CDC), reset synchronization, and timing analysis.
• Experience with high-speed interfaces such as PCIe, DDR4/DDR5, LPDDR4/LPDDR5, Ethernet, AXI, or CXL.
• Familiarity with simulation tools such as Questa, VCS, or Xcelium.
• Experience with scripting using Python, Tcl, or Bash.
• Strong debugging and problem-solving skills.

Responsibilities

• Design and implement FPGA-based prototypes for ASIC validation and feature development.
• Develop RTL in Verilog for FPGA implementation.
• Integrate IPs such as DDR, PCIe, Ethernet, CXL, or HBM into FPGA platforms.
• Perform FPGA synthesis, place-and-route, timing closure, and resource optimization.
• Debug FPGA designs using embedded logic analyzers, simulation, and hardware instrumentation.
• Develop board bring-up and validation plans for FPGA platforms.
• Create automation scripts for build, regression, and deployment flows using Python, Tcl, or Bash.
• Collaborate with architecture, RTL, verification, firmware, and post-silicon teams to resolve issues.
• Drive FPGA methodology improvements, coding standards, and design best practices.

Skills

FPGA design & implementation

Verilog/SystemVerilog

Altera Quartus Prime Pro

CDC/Timing analysis

High-speed interfaces

Scripting (Python/Tcl/Bash)

Debugging & problem solving

Education

BS/MS in Electrical/Computer Engineering or related

Tools

Questa

VCS

Xcelium

Quartus Prime Pro

Job description

Job Details

We are seeking an experienced FPGA Design Engineer to develop FPGA-based solutions for pre-silicon validation, hardware prototyping, and high-speed interface verification. The ideal candidate will have a strong digital design background, hands-on FPGA implementation experience, and expertise in high-speed protocols and memory interfaces. This role involves close collaboration with design, verification, firmware, and post-silicon validation teams to accelerate product development and improve design quality.

Key Responsibilities

• Design and implement FPGA-based prototypes for ASIC validation and feature development.
• Develop RTL in Verilog for FPGA implementation.
• Integrate complex IPs such as DDR, LPDDR, PCIe, Ethernet, CXL, or HBM into FPGA platforms.
• Perform FPGA synthesis, place-and-route, timing closure, and resource optimization.
• Debug FPGA designs using embedded logic analyzers (SignalTap), simulation, and hardware instrumentation.
• Develop board-level bring-up and validation plans for FPGA platforms.
• Create automation scripts for FPGA build, regression, and deployment flows using Python, Tcl, or Bash.
• Collaborate with architecture, RTL, verification, firmware, and post-silicon teams to resolve functional and performance issues.
• Drive FPGA methodology improvements, coding standards, and design best practices.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of FPGA design and implementation experience.
• Strong proficiency in Verilog/SystemVerilog and digital logic design.
• Experience with Altera Quartus Prime Pro development environments.
• Experience with FPGA synthesis, timing closure, and implementation.
• Strong understanding of clock domain crossing (CDC), reset synchronization, and timing analysis.
• Experience with high-speed interfaces such as PCIe, DDR4/DDR5, LPDDR4/LPDDR5, Ethernet, AXI, or CXL.
• Familiarity with simulation tools such as Questa, VCS, or Xcelium.
• Experience with scripting using Python, Tcl, or Bash.
• Strong debugging and problem-solving skills.

Preferred Qualifications

• Experience with FPGA-based emulation or ASIC prototyping.
• Knowledge of high-speed SerDes architectures.
• Experience with memory controllers and PHY interfaces.
• Familiarity with UVM-based verification environments.
• Experience with board bring-up, oscilloscopes, protocol analyzers, and logic analyzers.
• Knowledge of embedded processors (ARM, Nios II/V) is a plus.

What Youll Bring

• Excellent analytical and debugging skills.
• Ability to work effectively across architecture, RTL, validation, firmware, and software teams.
• Strong communication skills and the ability to drive technical discussions.
• Ownership mindset with the ability to deliver high-quality solutions in a fast-paced environment.

Job Type: Regular Shift: Shift 1 (India) Primary Location: Bengaluru, Karnataka, India Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.