Lead Analog Mixed Signal Verification Engineer

Ciliconchip; Bangalore Rural; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Ciliconchip is seeking an experienced AMS verification engineer to run and debug SPICE-based and mixed-domain simulations for AMS/SoC IPs. You will review test conditions, analyze waveforms, and resolve analog/digital interface issues in a collaborative team.

Leadership of a small team is required. The role requires strong fundamentals in analog/digital concepts, hands-on SPICE/digital simulation, and proficiency with WaveView or similar tools.

Qualifications

• 5 to 8 years of experience in AMS verification, simulation or debugging.
• Strong fundamentals of analog and digital concepts.
• Hands-on experience with SPICE and digital simulation tools and debug environments.
• Proficient in Verilog/SystemVerilog test/control and connectivity modeling.

Responsibilities

• Run and debug SPICE-based and digital simulations for AMS/SoC IPs and subsystems.
• Review simulation setups and ensure test conditions reflect design intent.
• Analyze waveform results to identify root causes of functional mismatches.
• Collaborate with designers to resolve analog/digital interface and model issues.
• Speed up debug and improve verification turnaround time through workflows and scripts.
• Document verification findings and methodology updates.
• Supervise and lead a small team of engineers (5–10).

Skills

AMS verification

Analog & Digital fundamentals

Verilog/SystemVerilog

WaveView

Collaboration

Tools

Synopsys XA

Cadence DiscoveryAMS

SPICE

Job description

• Run and debug SPICE-based and digital simulations for AMS/SoC IPs and subsystems.
• Understand analog and digital design intent, review simulation setups, and ensure correct test conditions.
• Analyze results using waveform/debug tools and identify root cause for functional mismatches.
• Work with designers to resolve analog/digital interface issues, model issues, and corner-case failures.
• Use simulation and waveform tools to speed up debug and improve verification turnaround time.
• Contribute to improving simulation workflows (run scripts, log parsing, automation, regression stability).
• Support mixed domain / co-simulation activities where applicable (e.g., SPICE + digital).
• Document verification findings, debug notes, and simulation methodology updates.
• Supervise, train, lead small team of 5 to 10 engineers

Required Qualifications:

• 5 to 8 years of relevant experience in AMS verification / simulation / debug.
• Strong fundamentals of Analog and Digital concepts. Good working knowledge of Verilog / SystemVerilog concepts (test/control, connectivity, modeling).
• Hands-on experience with SPICE and digital simulation tools and debug environments.
• Ability to understand simulation environments and debug analog/digital design-related issues.
• Comfortable working in a collaborative team setup with clear communication.
• Waveform/Analysis: WaveView (or equivalent)
• AMS verification Tools (Synopsys XA, Cadence DiscoveryAMS)