AMS Verification Engineer

Silicon Patterns Pvt. Ltd.; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Silicon Patterns Pvt. Ltd. is seeking AMS Verification engineers with 3+ years of experience to drive verification planning and AMS SPICE testbench development for complex SoCs.

The role emphasizes strong analog/mixed-signal fundamentals, exposure to PM, PLLs, ADC/DAC, and clocking challenges. Proficiency with Cadence Virtuoso, SimVision, Verisium, and Xcelium is required. The ideal candidate will debug convergence issues, optimize simulation performance, and collaborate with cross-functional

Qualifications

• 3+ years of experience in AMS verification or analog/mixed-signal verification.
• Strong understanding of analog design fundamentals and mixed-signal architectures.
• Exposure to complex SoC integrations involving Power Management, PLL/Synthesizers, ADC/DAC, Bandgap references, Oscillators/Clocking, SerDes, and related digital control systems.
• Proven experience in verification planning, AMS SPICE testbench development, and debugging convergence issues.
• Hands-on experience with Cadence Virtuoso for schematic capture and waveform analysis tools such as SimVision/Verisium.
• Expertise with SPICE/Fast-SPICE simulators (Spectre, UltraSim, APS, XPS) and digital simulators (Cadence Xcelium/DMSO).
• Strong track record in debugging and optimizing AMS simulations, including convergence and stability across analog-digital boundaries.

Responsibilities

• Plan and execute AMS verification strategies for complex SoCs.
• Develop AMS SPICE testbenches and diagnose convergence issues.
• Analyze waveform data using Cadence tools like Virtuoso, SimVision, and Verisium.
• Optimize simulation performance and resolve environment/setup challenges.
• Collaborate with design teams on analog/digital integration topics.

Job description

We are looking for AMS Verification engineers.

Experience: 3+ Years

Notice Period: Immediate

Please find the below Job Description and details:

Technical Expertise:

Strong understanding of analog design fundamentals and mixed-signal architectures, with exposure to complex SoC integrations involving Power Management, PLL/Synthesizers, ADC/DAC, Bandgap references, Oscillators/Clocking, SerDes, and related digital control systems.

Proven experience in verification planning, AMS SPICE testbench development, and debugging complex convergence issues.

Hands-on experience with Cadence Virtuoso for schematic capture and waveform analysis tools such as SimVision/Verisium.

Simulation Tools:

Expertise in SPICE/Fast-SPICE simulators (Spectre, UltraSim, APS, XPS) and digital simulators (Cadence Xcelium/DMSO).

Test Development:

Debug & Optimization Skills:

Strong track record in resolving complex AMS simulation challenges, including environment/setup issues, runtime optimization, convergence at AMS boundaries, analog-digital integration, loading, and stability concerns.