AMS Verification Engineer - SPICE / Spectre / Virtuoso (Mixed-Signal)

Rvega; Bengaluru; Hybrid; INR 2,500,000 - 4,000,000; Full time

Job summary

RVega is seeking an experienced AMS Verification Engineer in Bengaluru to verify complex mixed-signal SoCs using SPICE and Fast-SPICE simulations at block, subsystem and chip-top levels.

You will build self-checking AMS testbenches, debug convergence issues at analog-digital boundaries, and optimize simulation runtime for large designs while collaborating with system architects, analog and digital DV teams.

Qualifications

• 5+ years in AMS SPICE simulation and verification.
• Strong analog fundamentals and mixed-signal architectures.
• SoC analog block integration: PM, PLLs, ADCs/DACs, bandgap references, oscillators and SerDes.
• Hands-on Cadence Virtuoso and waveform analyzers (SimVision/Verisium).

Responsibilities

• Plan and execute AMS verification at block, subsystem and chip-top level.
• Build AMS SPICE testbenches and robust, self-checking testcases.
• Debug convergence, loading, stability issues in mixed-signal simulations.
• Optimize simulation runtime for large mixed-signal designs.
• Collaborate with system architects, analog and digital designers, and DV teams on analog-digital integration.

Skills

AMS SPICE verification

Verification planning

Testbench development

Cadence Virtuoso

SimVision

Verisium

Spectre/APS/XPS/UltraSim

Digital analog integration

Tools

Cadence Virtuoso

SimVision

Verisium

Spectre

APS

XPS

UltraSim

Xcelium

DMS

Job description

Job description

RVega is hiring on behalf of a semiconductor design services company in Bengaluru for experienced AMS Verification Engineers to verify complex mixed-signal SoCs through SPICE and Fast-SPICE simulation at block, subsystem and chip-top level.

What you will do

• Plan and execute AMS verification at block, subsystem and chip-top level.


• Build AMS SPICE testbenches and robust, self-checking testcases.


• Debug complex simulation issues: convergence at analog-digital boundaries, loading, stability, and environment or setup problems.


• Optimise simulation runtime and setup for large mixed-signal designs.


• Work with system architects, analog and digital designers, and DV teams on analog-digital integration.

What we are looking for

• 5+ years of industry experience in AMS SPICE simulation and verification.


• Strong analog design fundamentals and understanding of mixed-signal architectures.


• Exposure to SoC integration of analog blocks: power management, PLLs and synthesisers, ADCs and DACs, bandgap references, oscillators and clocking, and SerDes.


• Hands-on experience with Cadence Virtuoso (schematic capture) and SimVision or Verisium (waveform analysis).


• Expertise in SPICE and Fast-SPICE simulators (Spectre, APS, XPS, UltraSim) and digital simulators (Xcelium, DMS).


• Proven experience in verification planning, testbench development and convergence debug.

Good to have

• Verification experience on PLLs, SerDes or high-speed I/O IP.


• Experience working across both analog design and digital verification teams.