AMSV Lead Engineer

Cyient; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Benefits offered by this job

Health insurance

Job summary

Cyient in Bengaluru, India, is seeking an experienced verification engineer to drive AMS simulations and verification flows. You will develop methodologies, review specs, and manage netlists and BOMs while collaborating with analog and digital design teams.

You will run SPICE-based and digital simulations for AMS SOCs/IPs, build regression suites, and optimize testbenches in Xcelium, Cadence, or Synopsys. Strong debugging skills and ability to document findings are essential.

Responsibilities

• Develop AMS simulation methodologies/flows (AXUM, AVUM, UVM-AMS).
• Manage and review specifications; develop verification plan.
• Manage BOM and netlist generations.
• Interact with cross-functional teams (analog and digital design) to manage updates from analog and RTL.
• Plan work distribution; own critical tasks for hands-on execution.
• Run and debug SPICE-based and digital simulations for AMS SOC/IPs and subsystems.
• Understand analog and digital design intent; review simulation setups and ensure correct test conditions.
• Analyze results using waveform/debug tools; identify root causes of functional mismatch.
• Use simulation and waveform tools to speed up debugging and improve verification turnaround time.
• Create and manage regression setup.
• Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS; optimize testbenches in Xcelium, Cadence, or Synopsys flows.
• Contribute to improving simulation workflows (run scripts, log parsing, automation, regression).
• Document verification findings, debug notes and simulation methodology updates.
• Contribute to team success by debugging sessions, providing insights, supervising, training and maintaining effective communication.

Tools

Xcelium

Cadence

Synopsys

Job description

• Development of AMS simulation methodologies/flows (AXUM, AVUM , UVM-AMS).
• Manage and Review specifications, developing verification plan.
  Manage BOM, netlist generations.
• Interacting with cross functional teams (analog design, digital design) to manage and track updates from and analog and RTL.
• Plan work distribution in the team and own up few of the critical tasks for hands on execution
  Run and debug SPICE based and digital simulations for AMS SOC/IPs and subsystems
  Understand analog and digital design intent, review simulation setups and ensure correct test conditions.
  Analyze results using waveform/debug tools and identify root cause for functional mismatch
• Use simulation and waveform tools to speed up debug and improve verification turnaround time
• Create and manage regression setup
• Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS, and optimize testbenches in tools like Xcelium, Cadence, or Synopsys flows.
• Contribute to improving simulation workflows (run scripts, log parsing, automation, regression)
• Document verification findings, debug notes and simulation methodology updates
• Contribute to the overall success of the team by actively participating in debugging sessions, providing valuable insights, supervise, train and maintaining effective communication within the team.