ASIC Design Verification Engineer

Cisco

Bengaluru

On-site

INR 1,500,000 - 2,000,000

Full time

14 days+

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Job summary

Cisco in Bengaluru, India is looking for a skilled ASIC Design Verification Engineer with over 7 years of experience in ASIC design verification. The candidate will architect and develop DV environments, create test plans, and ensure complete verification coverage. Proficiency in UVM/System Verilog is necessary, along with strong collaboration skills. This role offers the opportunity to work on innovative silicon technology and develop industry-leading chips in a dynamic environment.

Qualifications

7+ years of related ASIC design verification experience.
Proficient in verifying sophisticated blocks, clusters, and top level for ASIC.
Hands-on experience with System Verilog constraints, structures, and classes.

Responsibilities

Architect DV environment infrastructure.
Develop DV infrastructure from scratch.
Develop test plans and tests for qualification at various levels.
Collaborate closely with various teams for seamless integration.

Skills

ASIC verification using UVM/System Verilog

Verifying sophisticated blocks and clusters for ASIC

Building test benches from scratch

Scripting experience with Perl and/or Python

Education

Bachelor’s Degree in EE, CE, or related field

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Meet The Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best‑of‑breed silicon from Top of Rack (TOR) switches all the way through web‑scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground‑breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi‑functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

Your Impact

You will contribute to developing Cisco’s progressive data center by crafting industry‑leading sophisticated chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

Architect block, cluster and top‑level DV environment infrastructure.
Develop DV infrastructure from scratch.
Maintain and improve existing DV environments.
Develop test plans and tests for qualifying design at block, cluster and higher‑level environments with mix of constraint random and advised stimulus.
Ensure complete verification coverage through implementation and review of code and functional coverage.
Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist.
Collaborate closely with designers, architects, and software teams to address and debug issues during post‑silicon bring‑up, ensuring seamless integration and efficient performance.
Support testing of design in emulation.
Lead all aspects of and manage the ASIC bring‑up process.

Minimum Qualification

Bachelor’s Degree or equivalent experience in EE, CE, or other related field.
7+ years of related ASIC design verification experience.
Proficient in ASIC verification using UVM/System Verilog.
Proficient in verifying sophisticated blocks, clusters and top level for ASIC.
Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.

Preferred Qualifications