Sr. Staff ASIC Design Engineer

Synaptics Incorporated; Bengaluru Urban; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Synaptics Incorporated in Bengaluru seeks a Sr. Staff ASIC Design Engineer to lead complex ASIC/SoC design efforts from architecture to tape-out, mentoring peers and driving silicon bring-up.

The role requires deep RTL expertise, UPF-based power design, and strong collaboration across hardware, firmware, and software teams, with emphasis on quality and efficiency.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of ASIC/SoC design experience with increasing levels of technical ownership.
• Proven track record delivering complex ASIC/SoC designs through tape‑out and silicon.
• Hands‑on experience with WiFi/Bluetooth SoCs is a strong plus.
• Experience with low‑power design and UPF‑based methodologies.
• Proficient with industry‑standard EDA tools (Synopsys, Cadence, Mentor and/or Siemens).
• Hands‑on experience with Lint, CDC, synthesis, Formal, DFT, and static timing analysis.
• Familiarity with hardware/firmware/software interactions, system integration, and FPGA/emulation, and silicon bring‑up.
• Working knowledge of physical design, timing closure, power integrity, and PPA optimization.
• Demonstrated ability to work independently on complex issues with strong technical judgment.
• Strong scripting and automation capabilities using Python, Perl, Tcl, and/or shell scripting.
• Minimal travel up to 10%.

Responsibilities

• Contribute to SoC architecture, micro-architecture, design partitioning, system interfaces, clock/reset architecture, SoC integration, and RTL design of complex ASIC/SoC blocks from specification through tape-out and silicon bring-up
• Drive design tradeoffs across power, performance, area, cost, and schedule and recommend practical solutions based on system and product requirements
• Provide technical leadership for RTL design, lint, CDC/RDC, synthesis, timing constraints, and design‑quality closure
• Develop and implement low‑power architecture and methodologies, including UPF, power domains, isolation, retention, and power sequencing; Drive Power Analysis at chip‑level
• Work closely with Verification teams to define verification requirements, debug complex failures, and drive functional and coverage closure.
• Lead technical resolution of complex pre‑silicon and post‑silicon issues, using structured root‑cause analysis across hardware, firmware, and software boundaries.
• Develop and improve design methodologies, automation, and engineering flows to improve quality, productivity, and scalability.
• Participate in design reviews, documentation, and process improvements to ensure quality and efficiency
• Chip and IP level timing analysis and closure, timing constraint/SDC development
• Provide technical guidance and mentorship to junior engineers, contributing to team knowledge and best practices

Skills

RTL design

SoC integration

AXI/AHB

Python scripting

EDA tools

UPF power

Timing analysis

Scripting (Python, Tcl, Perl)

Mentorship

Education

Bachelors in Electrical/Computer Engineering or related

Tools

Synopsys

Cadence

Mentor Graphics

Siemens

Job description

Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world’s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra™ AI-Native embedded compute, Veros™ wireless connectivity, and multimodal sensing solutions. We’re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world’s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra™ AI-Native embedded compute, Veros™ wireless connectivity, and multimodal sensing solutions. We’re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Overview

Synaptics is seeking a Sr. Staff ASIC Design Engineer to join our growing team. The ideal candidate will bring strong ASIC/SoC design expertise, lead complex design and integration activities, and collaborate across cross-functional engineering teams. This role will contribute to architecture and methodology decisions, drive technical execution from design through tape-out and silicon bring-up, and mentor other engineers. This position reports to the Sr. Director, ASIC Design.

Responsibilities & Competencies

Job Duties

• Contribute to SoC architecture, micro-architecture, design partitioning, system interfaces, clock/reset architecture, SoC integration, and RTL design of complex ASIC/SoC blocks from specification through tape-out and silicon bring-up
• Drive design tradeoffs across power, performance, area, cost, and schedule and recommend practical solutions based on system and product requirements
• Provide technical leadership for RTL design, lint, CDC/RDC, synthesis, timing constraints, and design‑quality closure
• Develop and implement low‑power architecture and methodologies, including UPF, power domains, isolation, retention, and power sequencing; Drive Power Analysis at chip‑level
• Work closely with Verification teams to define verification requirements, debug complex failures, and drive functional and coverage closure.
• Lead technical resolution of complex pre‑silicon and post‑silicon issues, using structured root‑cause analysis across hardware, firmware, and software boundaries.
• Develop and improve design methodologies, automation, and engineering flows to improve quality, productivity, and scalability.
• Participate in design reviews, documentation, and process improvements to ensure quality and efficiency
• Chip and IP level timing analysis and closure, timing constraint/SDC development
• Provide technical guidance and mentorship to junior engineers, contributing to team knowledge and best practices

• Strong digital design background with expertise in RTL (Verilog/SystemVerilog) and SoC integration
• Familiar with SOC architecture and bus protocol including AXI/AHB
• Basic scripting skills and familiar with Python, TCL, Perl, etc.
• Ability to communicate complex, interactive design concepts clearly
• Proactive, self‑starter, able to work independently in a fast‑paced environment to complete projects on time with minimal guidance
• Well organized with strong attention to detail; proactively ensures work is accurate
• Positive attitude and work ethic; unafraid to ask questions and explore new ideas
• Resourceful and able to solve complex problems through adaptation of existing technology and investigation of new technology with a solid understanding of product architecture
• Analytical and able to make informed decisions based on experience
• Sets clear expectations and objectives, and brings parties together to drive key initiatives
• Ability to work within a diverse team and mentor developing team members
• Excellent verbal and written communication skills
• Strong collaboration skills, with the ability to influence technical decisions across engineering teams

Qualifications (Requirements)

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field or equivalent
• 12+ years of ASIC/SoC design experience with increasing levels of technical ownership
• Proven track record delivering complex ASIC/SoC designs through tape‑out and silicon
• Hands‑on experience with WiFi/Bluetooth SoCs is a strong plus
• Experience with low‑power design and UPF‑based methodologies
• Proficient with industry‑standard EDA tools (Synopsys, Cadence, Mentor and/or Siemens)
• Hands‑on experience with Lint, CDC, synthesis, Formal, DFT, and static timing analysis
• Familiarity with hardware/firmware/software interactions, system integration, and FPGA/emulation, and silicon bring‑up
• Working knowledge of physical design, timing closure, power integrity, and PPA optimization
• Demonstrated ability to work independently on complex issues where significant technical judgment and evaluation of multiple factors are required
• Strong scripting and automation capabilities using Python, Perl, Tcl, and/or shell scripting
• Minimal travel up to 10%

Belief in Diversity Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.