IP/SOC Design Engineer

Ciliconchip; Pune District; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Ciliconchip in Pune, India seeks an experienced engineer with 8–10 years in digital logic design, ARM cores, and IP/SoC verification to drive SoC integration and ensure design quality.

You will contribute to the complete SoC design flow, perform RTL coding, lead sign-offs, and support FPGA validation and post-silicon bring-up while working with wireless networking tech and cross-functional teams.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 8 to 10 years of experience in digital logic design and integration involving ARM cores, bus protocols, and interconnect architectures.
• Strong expertise in microarchitecture development, Verilog RTL coding, and IP/SoC verification.
• Experience in subsystem development and/or SoC RTL integration.
• Proven experience performing LINT, CDC, and RDC sign-offs to ensure the highest design quality.
• Strong understanding of the complete SoC design flow, from high-level architecture through synthesis.
• Experience with Synopsys VCS, RTL simulators, Verdi, spyglass tools.
• Experience conducting IP integration reviews and backend (BE) report reviews to support concurrent engineering efforts.
• Hands-on laboratory experience with FPGA validation and post-silicon bring-up.
• Working knowledge of wireless technologies and standards, including Wi-Fi (IEEE 802.11), Bluetooth, IEEE 802.15.4, or other networking controller architectures and implementations is preferred.

Skills

Digital logic design

ARM cores

IP/SoC verification

Verilog RTL coding

SoC RTL integration

LINT CDC RDC sign-offs

Complete SoC design flow

RTL simulators

Wireless networking knowledge

Education

Bachelor's or Master's in Electrical/Electronics

Tools

Synopsys VCS

RTL simulators

Verdi

SpyGlass

Job description

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 8 to 10 years of experience in digital logic design and integration involving ARM cores, bus protocols, and interconnect architectures.
• Strong expertise in microarchitecture development, Verilog RTL coding, and IP/SoC verification.
• Experience in subsystem development and/or SoC RTL integration.
• Proven experience performing LINT, CDC, and RDC sign-offs to ensure the highest design quality.
• Strong understanding of the complete SoC design flow, from high-level architecture through synthesis.
• Experience with Synopsys VCS, RTL simulators, Verdi, spyglass tools.
• Experience conducting IP integration reviews and backend (BE) report reviews to support concurrent engineering efforts.
• Hands-on laboratory experience with FPGA validation and post-silicon bring-up.
• Working knowledge of wireless technologies and standards, including Wi-Fi (IEEE 802.11), Bluetooth, IEEE 802.15.4, or other networking controller architectures and implementations is preferred.
• Self-motivated with a strong sense of ownership and the ability to drive issues to closure.
• Excellent written and verbal communication skills.
• Strong analytical and creative problem-solving abilities, including the capability to decompose complex problems into manageable components.