SoC Design Engineer

Best NanoTech; Hyderabad; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

Best NanoTech is seeking a senior SoC design engineer in Hyderabad to lead front-end design, RTL integration, and timing closure. You will work across ARM-based reference designs, work with Cadence/Primetime tools, and contribute to low-power strategies.

The role requires a Bachelor’s or Master’s in a related field and 6–8 years of experience in SoC design, with strong debugging skills and cross-functional collaboration across teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 6–8 years of experience in SoC or subsystem design.
• Strong knowledge of ARM architecture, AMBA protocols (AXI, AHB, APB), and system-level integration.
• Hands-on experience with Arm Corestone-based packages or similar ARM reference designs.
• Solid experience in ASIC front-end design, including RTL development and integration flows.
• Proficiency in Static Timing Analysis using Primetime or Cadence tools.
• Experience in ASIC synthesis, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) techniques using Spyglass.
• Familiarity with low-power design techniques, UPF, and tools like PowerArtist or Power Compiler (a plus).
• FPGA prototyping experience is desirable.
• Strong debugging skills across simulation, lint, CDC, and synthesis environments.
• Ability to collaborate in a fast-paced, cross-functional engineering environment

Responsibilities

• Collaborate in a fast-paced, cross-functional engineering environment.

Skills

ARM architecture

AMBA protocols (AXI, AHB, APB)

system-level integration

RTL development

Static Timing Analysis

ASIC synthesis

CDC

RDC

UPF (low-power)

PowerArtist/Power Compiler

FPGA prototyping

debugging (simulation, lint, CDC, S/S)

cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field

6–8 years of experience in SoC or subsystem design

Tools

Primetime

Cadence tools

Spyglass

Job description

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 6–8 years of experience in SoC or subsystem design.
• Strong knowledge of ARM architecture, AMBA protocols (AXI, AHB, APB), and system-level integration.
• Hands-on experience with Arm Corestone-based packages or similar ARM reference designs.
• Solid experience in ASIC front-end design, including RTL development and integration flows.
• Proficiency in Static Timing Analysis using Primetime or Cadence tools.
• Experience in ASIC synthesis, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) techniques using Spyglass.
• Familiarity with low-power design techniques, UPF, and tools like PowerArtist or Power Compiler (a plus).
• FPGA prototyping experience is desirable.
• Strong debugging skills across simulation, lint, CDC, and synthesis environments.
• Ability to collaborate in a fast-paced, cross-functional engineering environment