IP Logic Design Engineer

NEWSOFT CONSULTANTS; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NEWSOFT CONSULTANTS is seeking an RTL Design Engineer to implement RTL from A-specs, perform IP RTL integration and sign-off on IP-level quality. The role includes quality checks such as functionality, lint, CDC, and synthesis, and requires defining RTL methodology, coding standards, simulation flows and a robust debug process.

Candidate should have deep PCIe/DDR/UCIE IP architecture experience and strong SystemVerilog/RTL coding skills, with emphasis on clock-domain crossing and STA debugging.

Qualifications

• Strong RTL coding and verification skills.
• Proficiency in SystemVerilog for IP development.
• Experience with PCIe/ DDR architectures and AMBA/UCIE familiarity.

Responsibilities

• Implement RTL from architectural specs (A-specs).
• Integrate IP at RTL level and sign-off quality.
• Perform lint/CDC, synthesis checks, timing closure and regression tests.
• Define RTL methodology, coding standards, simulation flows and debug processes.

Skills

RTL design

SystemVerilog

PCIe arch

DDR arch

Lint

CDC

Timing analysis

Job description

Implement RTL Design from (A-specs) architectural specs. Execute IP RTL integration, IP level quality sign-off. Quality checks such as functionality, lint/CDC,synthesis checks. Define RTL methodology, coding standard, simulation flows, debug process

Required Candidate profile

• Deep PCIe/DDR/UCIE IP arch.
• Solid SystemVerilog, RTL coding, Clock domain crossing, microarch/simulation debug, STA.
• LINT, CDC/RDC, synthesis, timing, regression, code coverage. AMBA PCIe UCIe & DDR