Functional Verification Engineer

Accenture in India; Bengaluru; Vor Ort; INR 1.200.000 - 1.800.000; Vollzeit

Zusammenfassung

Accenture in India in Bengaluru is seeking a Functional Verification Engineer to develop and execute testbenches that verify digital designs at block and system levels. The role involves creating constrained-random, directed, and coverage-driven tests and collaborating with design teams to ensure robust verification before tape-out.

You will work with SystemVerilog and UVM, mentor colleagues, and drive verification strategies to achieve complete coverage in a fast-paced project lifecycle.

Qualifikationen

• 5+ years of experience in SoC verification.
• Experience with constrained-random, directed and coverage-driven tests.
• Proficiency in SystemVerilog and Universal Verification Methodology (UVM).

Aufgaben

• Act as SME and collaborate with multiple teams to lead verification efforts.
• Make and defend verification decisions and mentor junior engineers.
• Coordinate cross-functional reviews to align verification goals and deliverables.
• Provide practical solutions to problems for the team and across projects.

Kenntnisse

SoC Verification

SystemVerilog

UVM

Verification methodologies

Debugging

Ausbildung

15 years education

Tools

SystemVerilog

UVM

Jobbeschreibung

Project Role

Functional Verification Engineer

Project Role Description

Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

Must have skills

SoC Verification

Good to have skills

NA

Minimum experience

5 Year(s) Of Experience Is Required

Educational Qualification

15 years full time education

Summary

As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly validate the design. Collaboration with design and architecture teams is essential to identify potential corner cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across teams to maintain high-quality verification standards throughout the project lifecycle.

Roles & Responsibilities

• Expected to be an SME, collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Lead efforts to improve verification methodologies and processes to enhance efficiency and effectiveness.
• Mentor junior team members by providing guidance and support to foster their professional growth.
• Coordinate cross-functional reviews to ensure alignment on verification goals and deliverables.

Professional & Technical Skills

• Must To Have Skills: Proficiency in SoC Verification.
• Strong knowledge of verification methodologies including constrained-random testing and coverage-driven verification.
• Experience with SystemVerilog and Universal Verification Methodology for testbench development.
• Ability to analyze complex digital designs and develop effective verification strategies.
• Familiarity with simulation tools and debugging techniques to identify and resolve functional issues.
• Capability to work collaboratively with design and architecture teams to ensure comprehensive verification coverage.

Additional Information

• The candidate should have minimum 5 years of experience in SoC Verification.
• This position is based at our Bengaluru office.
• A 15 years full time education is required.