Functional Verification Engineer

IBM; Bengaluru; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

IBM in Bengaluru seeks an experienced ASIC Verification Engineer to drive verification across IBM SOCs and processors. You will stress test, identify corner cases, and verify high-speed interfaces and IP integration, ensuring robust design movement.

Applicants should have 9+ years in functional verification, strong HDL/UVM experience, and proficiency with Linux, Git, and automation tools to lead testbench development and triage complex failures.

Qualifications

• 9+ years of experience in functional verification of processors or ASICs.
• Experience with 3rd party IP blocks: DDR, PCI, NAND, AXI.
• Proficiency in HDL/verification methodologies (UVM/OVM/SystemVerilog).
• Strong debugging and triage skills; ability to lead verification efforts.
• Development on Linux/Unix, Git, and CI/CD workflows.

Responsibilities

• Stress testing and identify corner case scenarios.
• Verify high-speed SERDES and PHY; ensure IP/SoC integration aligns with specs.
• Understand computer and microarchitecture; develop verification plans.
• Lead verification of multiple IPs/blocks and overall SoC fabric.
• Develop complex testbenches, automation, and debug failures efficiently.

Skills

ASIC verification

Functional verification

UVM/OVM/SystemVerilog

HDL Verilog/VHDL

C/C++ & Python

IP/SoC integration

Clock domain / reset domain

Gate level simulation & emulation

Linux/Unix development

CI/CD workflow

Testbench development

Tools

Git

Linux/Unix

CI/CD tools

Verification testbench tooling

Job description

IntroductionAs a ASIC Verification Engineer , you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today’s market.

Your Role And Responsibilities

• Stress testing and ability to identify corner case scenarios.
• Knowledge of high-speed SERDES and PHY Verification.
• Good understanding of computer system architecture and microarchitecture.
• Knowledge in IP Integration and SoC level verification.
• Exposure to automation.

Required Technical And Professional Expertise

• Required Professional and Technical Expertise
• 9 + years of experience in Functional Verification of processors or ASICs.
• Minimum 9+ years of experience in any of the following Experience with 3rd party IP blocks: DDR, PCI, NAND, or AXI.
• Self-Starter, ready to move quickly to keep the design moving forward.
• IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc .AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification.
• Gate level simulation and emulation. Track record in leading team.
• Clock domain crossing and reset domain crossing verification .
• Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ .Knowledge of HDLs (Verilog, VHDL) .
• Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl.
• Worked on multiple levels of verification (unit/element/sub-system/system level).
• Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow.
• Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails

Preferred Technical And Professional Experience

• As a Functional verification engineer, you will be working on IBM SOC or ASICs used in IBM servers.
• Leading the development of the verification environment, testbenches and writing testcases.
• Develop skills in IBM Functional verification tools and methodologies.
• Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design.
• Work with development team to ensure coverage criteria is met.