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Accenture in Bengaluru seeks a Functional Verification Engineer to develop and execute testbenches that validate digital designs at block and system levels. The role emphasizes constrained-random, directed, and coverage-driven testing using SystemVerilog and UVM to ensure complete functional coverage before tape-out.
Collaboration with design and architecture teams is essential to identify corner cases and improve verification effectiveness.
Functional Verification Engineer
Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
SoC Verification
NA
5 year(s) of experience is required
15 years full time education
As a Functional Verification Engineer, a typical day involves developing and executing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role includes creating various types of tests, such as constrained-random, directed, and coverage-driven, to thoroughly validate the design. Collaboration with design and architecture teams is a key part of the day, focusing on identifying edge cases and ensuring that all functional aspects are covered before the final tape-out stage. This position requires a proactive approach to problem-solving and continuous communication across multiple teams to maintain design integrity throughout the verification process.
15 years full time education