Functional Verification Engineer

Accenture; Bengaluru; On-site; INR 1,800,000 - 3,800,000; Full time

Job summary

Accenture in Bengaluru seeks a Functional Verification Engineer to develop and implement testbenches ensuring the functional accuracy of digital designs at block and system levels. The role involves creating constrained-random, directed, and coverage-driven tests using SystemVerilog and UVM, and collaborating with design and architecture teams to identify corner cases before tape-out.

The position requires 8+ years of Design Verification Testing experience and 15 years of full-time education,

Qualifications

• Must have skills: Proficiency in Design Verification Testing.
• Strong knowledge of verification methodologies including constrained-random testing and coverage-driven verification.
• Experience with SystemVerilog and Universal Verification Methodology for testbench development.
• Ability to analyze complex digital designs and develop effective verification strategies.
• Familiarity with simulation tools and debugging techniques to identify and resolve functional issues.
• Excellent collaboration skills to work effectively with design and architecture teams.

Responsibilities

• Lead/ SME in verification; collaborate and manage the team to perform.
• Responsible for team decisions and engagement with multiple teams.
• Drive verification plans alignment with design specifications.
• Mentor junior members in verification methodologies and best practices.
• Coordinate cross-functional meetings to share knowledge and resolve challenges.
• Drive continuous improvement to enhance verification efficiency and effectiveness.

Skills

Design Verification Testing

Education

15 years full time education

Job description

Project Role : Functional Verification Engineer

Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.

Must have skills : Design Verification Testing

Good to have skills : NA

Minimum 7.5 year(s) of experience is required

Educational Qualification : 15 years full time education

Summary

As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive testbenches to ensure the functional accuracy of digital designs at both block and system levels. The role requires creating a variety of test scenarios, including constrained-random, directed, and coverage-driven tests, to thoroughly validate design functionality. Collaboration with design and architecture teams is essential to identify potential corner cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across teams to maintain high-quality verification standards throughout the project lifecycle.

Roles & Responsibilities

• Expected to be an SME, collaborate and manage the team to perform.
• Responsible for team decisions.
• Engage with multiple teams and contribute on key decisions.
• Provide solutions to problems for their immediate team and across multiple teams.
• Lead the development and review of verification plans to ensure alignment with design specifications.
• Mentor junior team members by providing guidance and support in verification methodologies and best practices.
• Coordinate cross-functional meetings to facilitate knowledge sharing and resolve verification challenges.
• Drive continuous improvement initiatives to enhance verification efficiency and effectiveness.

Professional & Technical Skills

• Must To Have Skills: Proficiency in Design Verification Testing.
• Strong knowledge of verification methodologies including constrained-random testing and coverage-driven verification.
• Experience with SystemVerilog and Universal Verification Methodology for testbench development.
• Ability to analyze complex digital designs and develop effective verification strategies.
• Familiarity with simulation tools and debugging techniques to identify and resolve functional issues.
• Excellent collaboration skills to work effectively with design and architecture teams.

Additional Information

• The candidate should have minimum 8 years of experience in Design Verification Testing.
• This position is based at our BDC6F - SEZ office.
• A 15 years full time education is required.

15 years full time education

Equal Employment Opportunity Statement

All employment decisions shall be made without regard to age, race, creed, color, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.

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