Front End RTL Design Automation Engineer

Pozibility Technologies; Bengaluru; On-site; INR 800,000 - 1,400,000; Full time

Job summary

Pozibility Technologies is seeking an experienced hardware verification professional with strong expertise in Verilog and SV, RTL design, and verification methodologies. The role requires hands-on experience in RTL and gate-level verification, UPF-based low-power verification, and RTL hand-off processes to backend teams.

Proficiency in scripting and strong communication are essential for collaboration. Ideal candidates hold a Bachelor or Master’s degree in Electronic/Electrical Engineering with

Qualifications

• Bachelor/Master's Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics.
• Well-versed in Verilog and SV with RTL design, verification and synthesis practices.
• Experience in RTL and/or gate-level verification domain.
• Proficient in verification methodologies: assertion, function and test coverage.
• Knowledge of UPF low-power design and verification methods.
• Experience with lint checks and IP hand-off to backend RTL hand-off to backend.
• Proficient in Perl, TCL, or Shell scripting.
• Good communication skills (written and verbal).

Skills

Verilog

SV

RTL design

Verification

UPF

RTL hand-off

Lint checks

IP/SoC integration

Backend RTL hand-off

Perl

TCL

Shell scripting

Communication skills

Education

Bachelor/Master's Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics

Tools

NC-Sim

Modelsim

VCS

Specman

Debussy

Verdi

Job description

• Well versed in Verilog and SV with good understanding of RTL design, verification and synthesis practices. Prior work experience in the RTL and/or gate level verification domain is a must.
• Well conversant with different verification methodologies like assertion, function and test coverage with good understanding of test generation process.
• Knowledge on low power design and verification methods using UPF is a must.
• Expertise in RTL quality sign-off through lint checks, IP to SoC integration, IP hand-off, constraints etc., RTL hand-off to backend.
• An expert user of one or more of the following verification tools: NC-Sim*, Modelsim*, VCS, Specman*, Debussyand/or Verdi
• Good automation skills in PERL and/or TCL and/or Shell*. Good communication skills (written and verbal).

Qualification:

Bachelor/Master s Degree in Electronic/Electrical Engineering with Major in VLSI/Microelectronics