Foundry PDK Design Enablement Engineer

Cadence Design Systems India Pvt Ltd; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Cadence Design Systems India Pvt Ltd in Bengaluru seeks a Design Engineer II with 2–4 years of experience in Foundry PDK design enablement. You will bridge process technology and design, driving PDK validation and automated flows for advanced nodes.

The role emphasizes strong fundamentals in device physics, LVS/DRC, and Spice models, with collaboration across PDK and DTCO teams to deliver robust technology enablement.

Qualifications

• 2–4 years of hands-on experience in semiconductor technology analysis and PDK enablement.
• Strong understanding of PDK design enablement flows.
• Experience with LVS, DRC, Parasitic Extraction and Spice models.
• Cadence-based tool knowledge is a plus.

Responsibilities

• PDK enablement: validate, deploy, and maintain foundational PDK components for advanced nodes.
• Technology study activities: benchmark standard cells, SRAM, and custom circuits for PPA.
• Automation & methodology: develop scripts and flows for PDK enablement/validation.
• Collaborate with DTCO groups to translate advanced device architectures into reality.

Skills

PDK Enablement

LVS/DRC/Parasitic Extraction

Spice models

CMOS device physics

Cadence tools

Education

Bachelor’s or Master’s degree in Electronics / Electrical Engineering / VLSI / Microelectronics / Semiconductor Technology

Tools

Cadence tool suites

Job description

Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Opportunity: Foundry PDK Design Enablement Engineer Experience Level: 2–4 Years Department: Methodology & Flow Enablement Group Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field Position Overview We are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2–4 years of experience to join our process technology group.

Job Details

• Job Opportunity: Foundry PDK Design Enablement Engineer
• Experience Level: 2–4 Years
• Department: Methodology & Flow Enablement Group
• Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field

Position Overview

We are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2–4 years of experience to join our process technology group. In this role, you will bridge the gap between process technology and design, driving next-generation semiconductor technology through cutting-edge path-finding methodologies. The ideal candidate possesses a strong foundation in PDK enablement, physical verification decks, process/design interaction electrical studies, Spice model understanding and design automation.

Key Responsibilities

• PDK Enablement: Validate, deploy, and maintain foundational PDK components specifically tailored for advanced technology nodes.
• Technology Study Activities: Conduct rigorous standard cell, SRAM, and custom circuit benchmarking alongside interconnect optimization to maximize power, performance, and area (PPA).
• Automation & Methodology: Design, develop, and maintain robust scripts and automated execution flows for PDK enablement/validation and PDK analysis.
• Collaborative Path-Finding: Partner closely with internal DTCO groups to turn advanced device architectures into reality.

Required Qualifications & Technical Skills

• Industry Experience: 2–4 years of hands‑on experience in semiconductor technology analysis, foundry PDK enablement, and the co-optimization of PDK components like LVS, DRC, Parasitic Extraction, spice models.
• Strong understanding of PDK design enablement flows.
• Exposure to multiple foundry & nodes is a plus.
• Device Physics: Strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around), FinFETs, and planar MOSFETs.
• Physical Verification & EDA: Deep knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level.
• Cadence based tool knowledge is a plus.
• Tooling Familiarity: Direct experience or high proficiency with Cadence-based tool suites is highly advantageous.
• Team Collaboration: Proven experience interfacing with core PDK development teams, technology enablement units, or advanced technology benchmarking groups.

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