Senior EDA Engineer – Cadence Virtuoso, SKILL/CDF & OpenAccess

Best NanoTech; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Best NanoTech in Bengaluru is seeking a Senior EDA Engineer skilled in Cadence Virtuoso for analog/mixed-signal IC design and automation. You will drive schematic/layout workflows, develop SKILL scripts, and integrate OA APIs with PDK/CDK data, collaborating across AI/EDA and software teams.

You will work on updating and validating device libraries, pCells, and layout generators, ensuring robust design-data processes and efficient automation across the design flow.

Qualifications

• 3-10 years of hands-on experience with Cadence Virtuoso Analog/Mixed-Signal design flows.
• Strong Cadence SKILL scripting for schematic/layout automation.
• Experience creating and customizing CDF parameters / callbacks.
• Hands-on with OpenAccess Database API and OA schema.
• Programming/scripting in C++, Python and/or Tcl.
• Strong UNIX/Linux scripting and version-control knowledge.
• Familiarity with foundry PDK/CDK structures, pCells, symbols, and LVS/DRC workflows.

Responsibilities

• Develop, maintain, and optimize analog/mixed-signal IC design flows using Cadence Virtuoso.
• Create and optimize SKILL scripts for schematic, layout, and automation.
• Manage CDF parameters/callbacks for Cadence libraries and OA APIs.
• Build EDA automation utilities using C++, Python, and Tcl with OA APIs.
• Integrate and validate foundry PDK/CDK devices and DRC/LVS decks.
• Troubleshoot PDK integration, OA data integrity, and EDA environment issues.
• Collaborate with AI/EDA and software teams on design automation platforms.

Skills

Cadence Virtuoso

Analog/Mixed-Signal design

SKILL scripting

CDF customization

OpenAccess APIs

C++

Python

Tcl

UNIX/Linux

Git/SOS version control

Tools

Cadence Virtuoso

OpenAccess OA

PDK/CDK integration tools

Job description

Work Mode: On Site

Experience: 3- 10 Years

Notice Period: Immediate to 30 Days

• Role Overview

We are looking for a Senior EDA Engineer with hands-on expertise in Cadence Virtuoso-based Analog/Mixed-Signal design environments, SKILL scripting, CDF customization, OpenAccess (OA) APIs, and foundry PDK/CDK integration.

The role will focus on developing and automating schematic, layout, simulation, verification, and design-data workflows while collaborating with AI/EDA and software development teams on advanced design automation. 3. Required Qualifications 4. Technical Skills

• Key Responsibilities
• Develop, maintain, and optimize Analog/Mixed-Signal IC design flows using Cadence Virtuoso and associated EDA tools.
• Develop and optimize SKILL scripts for schematic, layout, verification, and design-environment automation.
• Create, modify, and manage CDF parameters, configurations, and callbacks for Cadence device libraries.
• Work with OpenAccess (OA) database APIs to read, write, and manipulate schematic, layout, connectivity, and library data.
• Develop EDA automation utilities using C++, Python and/or Tcl with OpenAccess APIs.
• Build automation workflows supporting schematic/layout integration, PDK/CDK validation, design-data migration, and QA.
• Integrate and validate foundry PDK/CDK devices, pCells, symbols, DRC/LVS decks, and simulation models.
• Troubleshoot PDK integration, OA database consistency, schematic-layout synchronization, and EDA environment issues.
• Automate schematic, library, simulation, and design-data processing workflows.
• Develop reusable automation scripts and document technical processes and EDA workflows.
• Support simulation automation and extraction/processing of PSF or raw simulation data.
• Collaborate with AI and software teams to integrate EDA tools with AI-assisted analog design and automation platforms.
• 3- 10 years of hands-on experience with Cadence Virtuoso Analog/Mixed-Signal design flows.
• Strong expertise in Cadence SKILL scripting for schematic and layout automation.
• Proven experience creating and customizing CDF parameters / CDF callbacks.
• Hands-on experience with OpenAccess (OA) Database API and OA schema.
• Programming or scripting experience using C++, Python and/or Tcl.
• Strong understanding of foundry PDK/CDK structures and integration.
• Experience with pCells, symbols, device models, layout generators, and design-rule decks.
• Knowledge of LVS and Schematic Driven Layout workflows.
• Strong UNIX/Linux command-line and scripting skills.
• Experience with Git, SOS, or equivalent version-control systems used in EDA environments.
• Analog/Mixed-Signal IC Design Flows
• Schematic & Layout Environment
• Schematic Driven Layout
• LVS

EDA Automation

• Cadence SKILL
• SKILL Scripting
• CDF Parameters
• CDF Callbacks
• Schematic Automation
• Layout Automation
• Library Automation
• Simulation Automation

OpenAccess & Programming

• OpenAccess (OA) Database API
• OA Schema
• C++
• Python
• Tcl
• Shell Scripting

PDK / CDK

• Foundry PDK Integration
• CDK Integration
• Parameterized Cells (pCells)
• Layout Generators
• DRC/LVS Decks
PDK Validation
• Cadence Spectre
• ADE