Lead DFT Design Engineer

Cadence System Design and Analysis; Bengaluru; On-site; INR 1,800,000 - 3,600,000; Full time

Job summary

Cadence System Design and Analysis in Bengaluru seeks a skilled engineer to contribute to DFT, RTL implementation and verification, and EDA tooling integration. You will collaborate across geographies, mentor junior engineers and drive automation within complex silicon projects.

The role requires hands-on experience with Cadence Modus, Jasper lint tools, and scripting in Python/Tcl/Perl, with strong communication and problem-solving abilities.

Qualifications

• BE/B.Tech/M.E/M.Tech with 3+ years of relevant work experience and strong understanding of DFT concepts.
• Hands-on experience with industry standard EDA tools.
• Experience with logic simulators from one or more EDA vendors.
• Exposure to RTL2GDS flow, synthesis and scan insertion.
• Good communication and mentoring skills.

Responsibilities

• Collaborate with cross-functional teams across geographies to align on project deliverables.
• Mentor junior engineers and drive innovation and automation.
• Work on DFT methodology improvements and in-system test/debug activities.
• Exposure to post-silicon validation and ATE debugging is desirable.

Skills

DFT concepts

RTL design & verification

Scripting (Python/Tcl/Perl)

Mentoring

Communication

Education

BE/B.Tech or ME/M.Tech

Tools

Cadence Modus

Jasper RTL lint

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.
• Mentoring junior engineers and driving innovation/automation.
• BE/B.Tech/M.E/M.Tech with 3+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.
• Strong hands-on experience using industry standard EDA Tools.
• Experience with logic simulators from one or more EDA vendors.
• Experience on industry standard ATPG tools like Cadence Modus.
• Experience with RTL lint tools like Jasper.
• Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required.
• Programming in Perl/Tcl/Python or other scripting languages is a plus.
• Experience in post silicon validation, ATE debug and support is desired.
• Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.
• Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.