Experienced Engineer Top Level Verification

Ericsson; Bengaluru; On-site; INR 3,000,000 - 5,200,000; Full time

Job summary

Ericsson in Bengaluru is seeking an ASIC Top-Level Verification Engineer to join a team focused on high-performance verification of cutting-edge ASICs powering complex systems. You will work across RTL, SystemC/TLM, emulation, and silicon validation, contributing to test environments and robust verification strategies.

The role emphasizes hands-on debugging of SystemVerilog/VHDL, C test software, and multi-core architectures, with opportunities to influence verification methodologies and CI

Qualifications

• Solid C programming skills targeting ASICs or embedded software.
• Strong RTL debugging skills in SystemVerilog or VHDL simulations.
• Experience with SystemC/TLM simulation, hardware emulation, or silicon validation.

Responsibilities

• Develop SoC level test cases focusing on external interfaces and internal functionality.
• Prepare and set up designs to run in hardware emulators.
• Define and document verification strategies for ASIC components.
• Develop software driven tests written in C.
• Debug RTL designs with EDA simulation tools and SW debuggers.
• Debug failing test cases on SystemC/TLM platform, emulator, or silicon boards.
• Maintain CI regression across multiple platforms.

Skills

C programming

RTL debugging

SystemVerilog

VHDL

Tools

SystemC/TLM tools

Job description

About This Opportunity

Join our new ASIC top level verification team. We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As an ASIC Top‑Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security. You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.

What You Will Do

We are looking for people with focus in various areas in ASIC TLV. Exactly what you will do depends on your experience and the needs in the different projects, but typically includes

• SoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more.
• Preparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms.
• Participate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier. As input you have documents and information from interaction with various type of stakeholders.
• Participate in specification and development of software driven tests written in C.
• Debug RTL designs with help of EDA simulation tools and SW debuggers.
• But also debug failing test cases using the SystemC/TLM platform or using the hardware emulator, depending on the situation
• Beside RTL simulations you will debug failing test cases running on any of our other run-platforms, SystemC/TLM simulation, Hardware emulation and on Silicon mounted on boards in the lab. In case you lack experience of some platform you are expected to develop skills for such tasks.
• Contribute to keeping tests clean in the CI regression running on our four platforms.

You will bring

General skills you must possess

• Solid C programming skills targeting ASICs or other type of embedded software programming.
• Solid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs.

Desired knowledge and experience in

• Using SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC. Experience of multi core designs is a plus.
• GLS
• Coresight and other JTAG TAP related features
• Compiling designs for HW emulation
• Formal connectivity verification
• High speed interfaces like Ethernet, PCIe, CPRI
• ARM CPUs/cores, SMMU
• AMBA interconnect, preferably using Cadence STG or IWB

Soft Skills

• Open, inclusive mindset, embracing diversity in culture, nationality, gender, etc.
• Collaborative approach, with a focus on team productivity and mutual growth.
• Strong drive for innovation, with a proactive interest in refining verification methodologies.
• Clear communication skills for effective teamwork and coordination across diverse teams.

“All academic credentials must be from recognized and accredited institutions and are further subject to verification.”