Emulation Engineer

Object Technology Solutions; India; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Object Technology Solutions is seeking a senior hardware verification professional to drive pre-silicon validation for networking switches. You will define verification scope, build tests and emulation models, and collaborate with architecture, DV, and software teams to ensure comprehensive coverage.

You will leverage Zebu and Palladium for emulation, along with IXIA/Spirent traffic generators, and implement DPI transactors and coverage-driven verification to improve efficiency and reusable

Qualifications

• Develop pre-silicon test plans to validate switch features.
• Verify design and micro-architecture using emulation platforms.
• Build and test sub-systems and chip-level verification.
• Develop synthesizable design blocks and verification components.

Responsibilities

• Study chip architecture and micro-architecture for pre-silicon validation.
• Create and execute test plans using Tcl, Python and C/C++.
• Synthesize Verilog/SystemVerilog models for emulation platforms.
• Debug hardware and software issues across pre-silicon domains.
• Develop automation scripts and improve emulation methodologies.
• Establish robust emulation environments for global users.
• Collaborate with Architecture, DV, Design and Software teams.
• Define verification scope and infrastructure for networking switches.
• Work with architects and engineers to meet verification goals.
• Hands-on experience with Zebu, Palladium, IXIA, Spirent is desirable.

Skills

Python

C/C++

Verilog/SystemVerilog

Tcl/ITcl

DPI transactors

Assertions

Coverage-driven verification

Debugging

Networking switches

Tools

Zebu

Palladium

IXIA

Spirent

Job description

Job Description:

• "Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive pre-silicon test plans that thoroughly validate switch features."
• Verify the design, architecture, and micro-architecture using emulation platforms.
• Develop sub-system and chip-level tests using Tcl, ITcl, Python, and C/C++ to verify networking switch chips in emulation platforms.
• Build and synthesize Verilog/SystemVerilog-based models for emulation platforms such as Zebu or Palladium.
• Perform block, sub-system and chip/system-level debugging and root cause analysis for hardware and software issues, addressing pre-silicon challenges.
• Develop and optimize automation scripts and emulation methodologies to improve efficiency, reusability, and coverage.
• Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes.
• Build and maintain robust emulation environments that support a global user community.
• Collaborate closely with Architecture, Micro-Architecture, Design, DV, and Software teams to achieve comprehensive verification coverage and smooth project execution.
• Ability to define verification scope and contribute to the development of verification infrastructure for networking switches.
• Experience collaborating with architects, designers, and software engineers to achieve verification goals.
• Hands-on experience with emulation platforms (Zebu, Palladium), traffic generators (IXIA, Spirent), and high-speed interface protocols (e.g., PCIe, Ethernet) is desirable.
• Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification.