Emulation Engineer

Vhunt4u

Bengaluru

On-site

INR 900,000 - 1,400,000

Full time

4 days ago
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Job summary

Vhunt4u Group is looking for an experienced engineer to drive RTL design and verification efforts. The role focuses on emulation setups and debugging across Cadence Palladium, Synopsys ZeBu, and Siemens Veloce to validate complex chip designs before tape-out.

You will collaborate with design and verification teams to optimize performance, analyze debugging data, and ensure the emulated environment mirrors final product behavior.

Responsibilities

  • Expertise in RTL design and verification flows.
  • Expertise in hardware emulation platforms and FPGA Validation.
  • Expertise in emulation setup, compilation, and debugging.
  • Expertise in System Verilog and Verilog.
  • Expertise in configuring emulation platform tools such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce to validate hardware designs and accelerate debugging before tape-out.
  • Experience in performance analysis, debug, and resolving emulation issues.
  • Debug issues, run extensive test scenarios, and ensure the emulated system accurately mirrors the final products behaviour.
  • Collaborate with design and verification teams to optimize performance and reduce time-to-market for complex chip designs.

Job description

Responsibilities
  • Expertise in RTL design and verification flows.
  • Expertise in hardware emulation platforms and FPGA Validation.
  • Expertise in emulation setup, compilation, and debugging.
  • Expertise in with System Verilog and Verilog.
  • Expertise in configuring emulation platform tools such as Cadence Palladium, Synopsys ZeBu, or Siemens Veloce to validate hardware designs and accelerate debugging before tape-out.
  • Experience in performance analysis, debug, and resolving emulation issues.
  • Debug issues, run extensive test scenarios, and ensure the emulated system accurately mirrors the final products behaviour.
  • Collaborate with design and verification teams to optimize performance and reduce time-to-market for complex chip designs.
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