Emulation Engineer

Broadcom; Pune District; Presencial; INR 4.000.000 - 6.000.000; Jornada completa

Descripción de la vacante

Broadcom is seeking a senior verification engineer in Pune, India, to conduct pre-silicon studies and verification for ASICs using emulation platforms.

You will develop tests in Verilog/SystemVerilog, C/C++, Tcl, and Python, and build reusable verification components to streamline emulation processes. You’ll collaborate with Architecture, Design, DV, and FW teams to ensure comprehensive coverage and smooth project execution.

Formación

• Bachelor’s or Master’s degree in electrical engineering or related field.
• 8+ years of pre-silicon verification/emulation of ASICs.
• Define verification scope and contribute to verification infrastructure.
• Collaborate with architects, designers and software engineers to achieve verification goals.
• Strong Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation.
• Hands-on with emulation platforms (Zebu, Palladium), speed bridges, PCIe.
• Strong debugging skills; familiar with DPI transactors, assertions, coverage-driven verification.
• Verification engineers with simulation backgrounds are encouraged to apply.

Responsabilidades

• Study chip architecture and micro-architecture to define and execute pre-silicon test plans.
• Verify designs using emulation platforms and build tests in Tcl, Python, C/C++.
• Develop and optimize automation scripts and verification infrastructure.
• Create reusable verification components and models for emulation workflows.
• Collaborate with Architecture, Design, DV and FW/Validation teams to ensure coverage.
• Maintain robust emulation environments for a global user community.

Conocimientos

Verilog/SystemVerilog

C/C++

Tcl

Python

Scripting for automation

Zebu emulation

Palladium emulation

PCIe high-speed interfaces

DPI transactors & assertions

Collaboration with architects/teams

Educación

Bachelor's or Master's in Electrical Engineering

Herramientas

Zebu

Palladium

Speed bridges

Descripción del empleo

Job Description

Conduct detailed studies of chip architecture and micro-architecture to define, develop, and execute comprehensive pre-silicon test plans.

Verify the design, architecture, and micro-architecture using emulation platforms.

Develop sub-system and chip-level tests using Tcl, ITcl, Python, and C/C++ to verify chip designs in emulation platforms.

Build and synthesize Verilog/SystemVerilog-based models for emulation platforms such as Palladium.

Perform block, sub-system and chip/system-level debugging and root cause analysis for hardware and software issues, addressing pre-silicon challenges.

Develop and optimize automation scripts and emulation methodologies to improve efficiency, reusability, and coverage.

Create reusable synthesizable design blocks, libraries, and verification components to streamline emulation processes.

Build and maintain robust emulation environments that support a global user community.

Collaborate closely with Architecture, Design, DV, and FW/Validation teams to achieve comprehensive verification coverage and smooth project execution.

Requirements

Bachelor’s or Master’s degree in electrical engineering or related degree with 8+ years in pre-silicon verification/emulation of ASICs.

Ability to define verification scope and contribute to the development of verification infrastructure.

Experience collaborating with architects, designers, and software engineers to achieve verification goals.

Strong expertise in Verilog/SystemVerilog, C/C++, Tcl, Python, and scripting for automation.

Hands-on experience with emulation platforms (Zebu, Palladium), speed bridges, and high-speed interface protocols (e.g., PCIe) is desirable.

Strong debugging skills and familiarity with DPI transactors, assertions, and coverage-driven verification.

Verification engineers with simulation backgrounds are also encouraged to apply — strong verification fundamentals are highly valued.

Excellent communicator who thrives in a collaborative, fast-paced environment.

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