ASIC Emulation Engineer / Technical Leader

Cisco; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Cisco is seeking a professional to define, design, and develop emulation environments for networking ASICs in Bengaluru. You will work on developing state-of-the-art emulation infrastructure using C/C++ and scripting languages, ensuring robust testing and performance evaluation of multi-terabit systems. Candidates should have substantial experience with emulation platforms and a strong background in ASIC design and verification. This role requires excellent communication and teamwork skills to facilitate collaboration across various teams.

Qualifications

• Bachelors + 8 years of experience, or Masters + 6 years of experience.
• Experience with emulation platforms like Veloce, Palladium, Zebu.
• Fluent in SystemVerilog or Verilog.
• In-depth knowledge of C/C++ and ASIC design verification flows.

Responsibilities

• Develop emulation environments for performance and functionality evaluation.
• Collaborate with design and hardware teams for ASIC verification.
• Assist with test plan design and debugging during pre-silicon processes.

Skills

C/C++

SystemVerilog

Verilog

Python

Post-silicon validation

Education

Bachelor's degree

Master's degree

Tools

Veloce

Palladium

Zebu

GDB

Job description

Overview

Define, design and develop emulation environments needed for complex, large scale networking ASICs. Develop the emulation env, build netlists and use the same to speed up the development cycle and find potential ASIC issues during pre-silicon phase.

What You’ll Do

Develop state-of-the-art emulation environments that will be used to evaluate the performance and functionality of multi-terabit systems.

• Developing emulation infrastructure using C/C++ and TCL, Python, etc.
• Developing and testing various emulation flows and contributing to different aspects of ASIC verification for bug-free silicon.
• Collaborate closely with the design team and the hardware team to verify the ASIC in emulation and during ASIC bring-up.
• Work closely with the design, DV, power, and post-silicon diagnostic teams.
• Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process.
• Develop tests to generate complex traffic and performance scenarios to catch potential post-silicon issues during the pre-silicon phase.

Minimum Qualifications

• Bachelors + 8 years of related experience, or Masters + 6 years of related experience.
• Design emulation background with hands-on experience with emulation platforms like Veloce, Palladium, Zebu, as well as experience with compilation, debugging, and performance testing.
• Fluent in SystemVerilog or Verilog to work on the emulation infrastructure development work.
• In-depth knowledge of C/C++, scripting, as well as ASIC design and verification flow.
• Expertise in RTL development for emulation prototypes.
• System debug experience using tools like GDB and waveform debuggers.

Preferred Qualifications

• Strong hands-on experience with scripting programs (e.g., Python, Perl or similar).
• Strong communication skills and ability to work as a team.
• Post-silicon functional validation or debugging experience is a plus.
• Knowledge of protocols like PCIe, I2C, Ethernet.
• Good interpersonal skills and demonstrated leadership to describe issues and improvements and lead the team for on-time completion.
• Excellent communication skills both verbal and written.