Verification Lead

Tessolve; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Tessolve in Bengaluru area is hiring a Technical Lead for FPGA Verification (SV-UVM & DO-254). The role requires 9 to 18 years of hands-on experience in IP-based verification, including Communication IPs, Compute IPs, Memories, Graphics IP, and Security IP.

You will lead verification efforts, mentor junior engineers, and collaborate with cross-functional teams to ensure quality and on-time delivery in a full-time, on-site capacity.

Qualifications

• 9–18 years of hands-on FPGA verification experience.
• Experience with IP verification across communication, compute, memories, and graphics IPs.
• Strong knowledge of SV-UVM methodology and DO-254 standards.

Responsibilities

• Lead FPGA verification efforts across multiple IPs.
• Mentor and guide verification engineers and review test plans.
• Collaborate with design, validation, and project teams to ensure on-time delivery.

Skills

FPGA Verification

IP Verification

SV-UVM

Digital/Mixed-Signal Verification

Tools

SV-UVM

DO-254

Job description

Experience: 9 to 18 Years

Technical Lead - FPGA Verification (SV-UVM & DO-254)

• Communication IPs (including Ethernet)
• Compute IPs (CPU, DMA, Bus Infrastructure)
• Memories / NVM
• Graphics IP
• Security IP
• ADC Digital Part (Mixed Signal Verification)

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Information Technology

Industries

Semiconductor Manufacturing, Engineering Services, and IT Services and IT Consulting

Location

Greater Bengaluru Area