DV Engineers (Ethernet)

Honeybee Tech Solutions; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Honeybee Tech Solutions is seeking an ASIC Design Verification Engineer to join the Infrastructure team in Bangalore. The role focuses on building IP/SoC verification strategies for data center applications, including test planning, UVM-based bench development, simulation, formal verification, and emulation.

You will collaborate with cross-functional teams to ensure first-pass silicon success and contribute to verification methodology improvements while mentoring junior engineers.

Qualifications

• 5–9 years of experience in ASIC Design Verification.
• Strong expertise in SystemVerilog and UVM methodology.
• Experience with Verilog, C/C++ and Python-based verification.
• Strong understanding of AMBA protocols (AXI/APB).
• Hands‑on experience with Ethernet, PCIe, RDMA or other high‑speed protocols.
• Experience in IP, Cluster, and SoC‑level verification.
• Experience with RTL and Gate‑Level Verification.
• Strong debugging and root cause analysis skills.
• Experience in UVM‑based verification environment development from scratch.
• Knowledge of scripting languages such as Python, Perl, or TCL.
• Experience with verification tools, waveform debugging, and simulators.
• Experience using Git, Mercurial (Hg) or SVN.
• Strong understanding of networking and data center applications.

Responsibilities

• Develop and execute IP, subsystem, and SoC verification plans.
• Build UVM-based verification environments and functional test cases.
• Drive verification closure using functional and code coverage metrics.
• Debug and resolve design issues in collaboration with design teams.
• Perform functional, performance, and compliance testing.
• Work closely with Design, Emulation, Silicon Validation and Modeling teams.
• Mentor junior verification engineers and contribute to verification methodology improvements.
• Develop automated verification flows and infrastructure.

Skills

ASIC Design Verification

SystemVerilog

UVM

Verilog

C/C++

Python

AMBA AXI/APB

Ethernet

PCIe

RDMA

IP/SoC verification

RTL verification

Gate‑level verification

Debugging/root-cause analysis

Scripting (Python/Perl/TCL)

Git/Mercurial/SVN

Networking/Data center

Education

Bachelor's Degree in Computer Science/Computer Engineering

Tools

None

Job description

Job Details

• Position: DV Engineer (Ethernet)
• Experience: 5–9 Years
• Client: Knova One
• Location: Bangalore
• Work Type: Work From Office (WFO)
• Asset Requirement: Laptop Mandatory for Interview
• CVR Type: Internal CVR
• CVR Panel Name: Charitra
• Interview Rounds: 3
• Interview Mode: Microsoft Teams
• Shift: General Day Shift
• Department: Technical

About the Role

We are looking for an ASIC Design Verification Engineer to join the Infrastructure organization. The role involves building IP and System-on-Chip (SoC) solutions for data center applications. You will be responsible for verification closure of design modules and subsystems, including test planning, UVM-based testbench development, simulation, formal verification, and emulation.

You will collaborate with ASIC Design, Software, Hardware, Emulation, and Post-Silicon teams to ensure first-pass silicon success.

Key Responsibilities

• Develop and execute IP, subsystem, and SoC verification plans.
• Build UVM-based verification environments and functional test cases.
• Drive verification closure using functional and code coverage metrics.
• Debug and resolve design issues in collaboration with design teams.
• Perform functional, performance, and compliance testing.
• Work closely with Design, Emulation, Silicon Validation, and Modeling teams.
• Mentor junior verification engineers and contribute to verification methodology improvements.
• Develop automated verification flows and infrastructure.

Mandatory Skills

• 5–9 years of experience in ASIC Design Verification.
• Strong expertise in SystemVerilog and UVM methodology.
• Experience with Verilog, C/C++, and Python-based verification.
• Strong understanding of AMBA protocols (AXI/APB).
• Hands‑on experience with Ethernet, PCIe, RDMA, or other high‑speed protocols.
• Experience in IP, Cluster, and SoC‑level verification.
• Experience with RTL and Gate‑Level Verification.
• Strong debugging and root cause analysis skills.
• Experience in UVM‑based verification environment development from scratch.
• Knowledge of scripting languages such as Python, Perl, or TCL.
• Experience with verification tools, waveform debugging, and simulators.
• Experience using Git, Mercurial (Hg), or SVN.
• Strong understanding of networking and data center applications.

Preferred Skills

• Experience with DDR, HBM, ARM, RISC‑V, and 400G MAC verification.
• Knowledge of Formal Verification, SystemVerilog Assertions (SVA), and Emulation.
• Experience in AI/ML, Networking, or Video ASIC verification.
• Experience with automated verification flows and performance analysis.
• Strong collaboration skills across Design, Emulation, and Silicon Validation teams.

Educational Qualification

• Bachelor's Degree in Computer Science, Computer Engineering, or a related technical field (or equivalent practical experience).